2D Material Channel Structure With Bonded Gate Insulator Interface
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Solution Overview
Problem
As semiconductor devices decrease in size, the electrical characteristics of silicon-based channels are limited, necessitating improved materials and structures to enhance performance.
Innovation Solution
A semiconductor device is designed with channel structures featuring stacked 2D material layers, including a semiconducting transition metal dichalcogenide (TMD) and a second 2D material layer bonded with the gate insulation pattern through covalent or ionic bonds, enhancing adhesion and reducing charge trapping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon-based channels are used in semiconductor devices, then the devices can be manufactured with conventional processes, but the electrical characteristics are limited as device size decreases
Solution Approach 1:
The patent changes the material parameter from conventional silicon-based channels to 2D material channels (such as MoS2, WS2, MoSe2, WSe2), fundamentally altering the electrical characteristics and enabling continued scaling without the limitations of bulk silicon
Solution Approach 2:
The patent employs composite structures by stacking multiple 2D material layers (semiconducting 2D material layer combined with metallic 2D material layer or buffer layer) to achieve both electrical performance and structural stability
2Reliability
If 2D material layers are stacked to form channel structures, then mobility and adhesion are improved, but the device structure becomes more complex
Solution Approach 1:
The patent segments the channel structure into distinct functional layers: a semiconducting 2D material layer for charge transport and a metallic 2D material layer or buffer layer for adhesion and charge trapping reduction, with each layer optimized for its specific function
Solution Approach 2:
The patent introduces a buffer layer (metallic 2D material layer) as an intermediary between the semiconducting 2D material channel and the gate insulation pattern, which mediates the interaction by providing strong adhesion through covalent/ionic bonding while reducing charge trapping at the interface
3Reliability
If the second 2D material layer is bonded with the gate insulation pattern through covalent or ionic bonds, then adhesion is enhanced and charge trapping is reduced, but the manufacturing process becomes more difficult
Solution Approach 1:
The patent changes the bonding mechanism parameter from conventional weak van der Waals bonding to strong covalent or ionic bonding between the metallic 2D material layer and the gate insulation pattern, fundamentally improving the interface quality
Solution Approach 2:
The patent applies different bonding characteristics to different parts of the structure: the semiconducting 2D material layer maintains weak van der Waals bonding for easy stacking, while the metallic 2D material layer forms strong covalent/ionic bonds with the gate insulation pattern for enhanced adhesion and reduced charge trapping
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves increased mobility and reliability with reduced surface scattering, and improved adhesion between the channel and gate insulation pattern, leading to enhanced electrical characteristics.
Implementation Method 1
the second transition metal included in the second 2D material layer is bonded with an element included in the upper first gate insulation pattern by a covalent bond or an ionic bond
Implementation Method 2
the second transition metal included in the second 2D material layer is bonded with an element included in the upper first gate insulation pattern by a covalent bond or an ionic bond
Implementation Method 3
The device achieves increased mobility and reliability with reduced surface scattering
Data Source
AI summary
A semiconductor device includes channel structures spaced apart in a vertical direction; lower/upper first gate insulation patterns contacting lower/upper surfaces of the channel structures; a gate electrode surrounding lower/upper surfaces and a sidewall of the channel structures; and source/drain layers at sides of the gate electrode, wherein the channel structures include first/second 2D material layers stacked in the vertical direction, the first 2D material layer includes a semiconducting TMD including a first transition metal and first chalcogen elements that are bonded at lower/upper sides of the first transition metal, the second 2D material layer includes a second transition metal and a second chalcogen element, the second chalcogen element being bonded at a lower side of the second transition metal, and the second transition metal included in the second 2D material layer is covalently or ionically bonded with an element of the upper first gate insulation pattern.