2D Semiconductor Contact Structure for Lower Electrode Resistance
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing size while maintaining performance due to the limitations of traditional materials, particularly when scaling down to nanoscale thicknesses, where two-dimensional materials like transition metal dichalcogenides (TMDs) and black phosphorus show promise but require effective integration with electrodes to enhance electrical characteristics.
Innovation Solution
The semiconductor device design incorporates multiple layers of two-dimensional materials, including TMDs and black phosphorus, with strategically placed second two-dimensional material layers in planar contact with source and drain electrodes, surrounded by a gate insulating layer and gate electrode, and fabricated using edge epitaxy to reduce contact resistance and enhance electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two-dimensional materials are used to reduce device size, then the number of devices integrated on one wafer and driving speed increase, but contact resistance between materials and electrodes increases
Solution Approach 1:
The patent introduces a transition metal dichalcogenide (TMD) material layer as an intermediary between the semiconductor layer and metal electrodes. This TMD layer serves as a mediator that facilitates better electrical contact and reduces contact resistance, solving the interface compatibility problem between dissimilar materials while enabling high-density integration.
Solution Approach 2:
The patent employs composite material structures combining different two-dimensional materials (such as TMDs and black phosphorus) with metal electrodes. This composite approach leverages the advantageous properties of each material to achieve both low contact resistance and high integration density, addressing the contradiction between scalability and electrical performance.
2Volume of moving object
If device size is reduced to nanoscale thickness, then integration density increases, but electrical conductivity and performance deteriorate
Solution Approach 1:
The patent utilizes parameter changes by selecting TMD materials with specific bandgap properties (0.1 eV to 3.0 eV) and controlling their thickness at the nanoscale. By adjusting these parameters, the material maintains electrical conductivity even at reduced thickness, enabling high integration density without performance degradation.
Solution Approach 2:
The patent applies local quality by using different two-dimensional materials at different locations within the device structure. TMD materials are used specifically at the electrode interface where low contact resistance is critical, while other two-dimensional materials form the channel region. This spatial differentiation of material properties optimizes both conductivity and integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the electrical conductivity and reduces contact resistance between the two-dimensional material layers and electrodes, maintaining high mobility and performance even at nanoscale thicknesses, thereby addressing the performance degradation issues associated with downsizing semiconductor devices.
Implementation Method 1
fabricated using edge epitaxy to reduce contact resistance and enhance electrical connectivity
Data Source
AI summary
A semiconductor device may include at least one first two-dimensional material layer; a source electrode and a drain electrode that are respectively on both sides of the at least one first two-dimensional material layer; second two-dimensional material layers respectively on a side of the source electrode and a side of the drain electrode and connected to the at least one first two-dimensional material layer; a gate insulating layer surrounding the at least one first two-dimensional material layer; and a gate electrode on the gate insulating layer.