Nanoinformatics TRIZ Cases

By omitting the barrier layer between work function metals, this nano-FET gate stack reduces deposition defects while maintaining electrical performance.

A bottom dielectric self-aligns backside power rails in GAA structures to avoid gate shorts while increasing rail density and lowering resistance.

Selective etching of recessed semiconductor layers creates a T-shaped nanosheet channel that raises drive current without enlarging footprint.

An undulating diode topography with pedestal electrodes boosts carrier tunneling and current flow as device footprint shrinks.

Peripheral interbridge channels in nanosheet FETs cut concave corners, strengthen gate control, and raise on-current with lower leakage.

Selective cladding around the active channel widens the gate formation process window and keeps critical dimensions uniform in GAA transistors.

An asymmetric stacked nanosheet layout pairs gate-all-around channels with selective epitaxy to curb short-channel effects and raise device density.

Graded SiGe source/drain epitaxy fills recessed fins below the channel to improve strain efficiency, cut parasitic capacitance, and support scaling.

Removing dummy front-side S/D contact material to form a sealed air gap lowers gate-contact capacitance in backside power rail structures.

A halide precursor and reducing-agent route enables indium quantum dots with narrow size distribution, reproducible yield, and toxic-metal-free emission.

A PN junction replaces dielectric isolation in 3D stacked FETs, preventing source/drain shorts while simplifying epitaxial fabrication.

Ion implantation forms a virtual connecting layer that links same-layer 3D DRAM gates while isolating adjacent structures to cut leakage and process complexity.

Band alignment between the shell and barrier layer boosts TFET on-state current while limiting leakage and enabling lower-voltage operation.

A shaped upper semiconductor pattern and spacer increase gate-to-source/drain spacing to cut short-channel leakage and process defects.

Bottom dielectric isolation and substrate-contacted doped source/drains enable co-integrated nanosheet logic with low-leakage ESD clamping.

Metal oxide ALD densifies nanoimprint films to raise refractive index while improving hardness, strength, and etch resistance.

Undercutting the lower source/drain epi lets a bottom contact wrap multiple sidewalls, increasing contact area without enlarging footprint.

An insulating barrier between aligned 2D semiconductor layers sharpens NDR, improving detection of bandgap, quantum capacitance, temperature, and light.

Sculpted fin oxidation forms released nanowire channels so gate-all-around FETs gain stronger channel control at sub-10 nm nodes.

Overlapping POLY gate routing carries clock signals across active regions, reducing M0 use while improving routing flexibility and via access.

Nano-dot charge traps or a doped negative layer neutralize interface charges in bonded SOI substrates, reducing PSC, substrate loss, and distortion.

A tapered helmet dielectric fin improves source/drain patterning and gate formation while reducing parasitic capacitance and shorts.

Edge-epitaxial 2D contact layers between the channel and electrodes cut contact resistance while preserving nanoscale semiconductor mobility.

Perpendicular 2D contact layers cut contact resistance while preserving carrier mobility in ultra-thin semiconductor channels.

Low-k or air-gap inner spacers separate source-drain regions from the gate in GAA FETs, reducing parasitic capacitance at high frequencies.

A two-sided epitaxial cavity process improves quantum dot alignment and lattice control for scalable single-photon emitters or detectors.

A layered inner spacer uses an etch-stop dielectric plus low-k material to prevent etch-back defects and cut parasitic capacitance in GAA transistors.

Complementary FET stacking creates an intermediate supply voltage that speeds IC wake-up while preserving area efficiency and lowering power use.

Side-contact source/drain plugs create lower-resistance current paths in GAA transistors, reducing voltage drop and boosting channel current.

Different channel structures across substrate regions preserve transistor operating characteristics as semiconductor integration density increases.

Independently controlled etch zones improve CICE depth uniformity, sidewall quality, and collapse resistance in high aspect ratio semiconductor features.

Epitaxial single-crystal silicon oxide barriers in stacked MOSFET gates block dopant diffusion, improving reliability and etching selectivity.

Using ion implantation with a sacrificial liner, this case shows how a silicon-oxygen-carbon contact liner stabilizes dense fin contacts and reduces capacitance.

A sacrificial backside placeholder enables self-aligned nanosheet FET contacts from below, easing lithography alignment and expanding contact area.

Alternating oxygen and carbon monolayers in a semiconductor superlattice raise carrier mobility while limiting dopant diffusion and scattering.

A sloped spacer shapes a necked double-diamond source/drain to prevent shorts and expand silicide contact area, lowering resistance.

A non-linear germanium gradient in the source/drain region boosts channel compressive stress, improves hole mobility, and avoids an added layer.

A self-aligned gate isolation structure cuts gate endcap area in nanosheet FETs, easing contact scaling while improving density and performance.

Wet ammonia etching reshapes round semiconductor contact vias into square forms, increasing contact area for lower resistance and better heat flow.

Stacked SiGe buffer layers with graded Ge content cut source/drain resistance and growth defects, improving FinFET performance and reliability.

Conformal multi-silicide layers improve 3D GAA FET contact coverage, lowering resistance and supporting more reliable etch control.

Selective hardmask trimming creates a shorter gate on active nanosheets and a longer gate on STI to improve work function metal patterning.

Alternating Ge epitaxial layers and a gap-filling sixth layer cut source/drain defects while preserving channel compressive stress.

Silicon monolayers at the germanium quantum well interface boost hole Rashba coupling, enabling faster spin qubit control with CMOS compatibility.

A tuned dielectric cap and rounded gate-top profile cut parasitic capacitance and electrical shorts in self-aligned contacts.

An epitaxial insulating liner along the semiconductor liner sidewall improves current control and suppresses short-channel effects in scaled transistors.

A recessed notch in the lower CFET source/drain creates dielectric isolation between stacked epitaxial regions, preventing shorts and improving reliability.

Highly doped nanoribbons and SiGe/high-k layers enable backside varactor connections below 10 nm while improving Q and lowering resistance.

Self-aligned GAA nanostructures use asymmetric contact plugs and isolation gate stacks to preserve gate control while easing scaled contact fabrication.

A protective layer bridges source/drain regions and stacked channel layers to expand contact area, cut resistance, and improve semiconductor operation.