Semiconductor Liner Sidewall Insulation for Short-Channel Control
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Solution Overview
Problem
Current semiconductor devices face challenges in scaling and improving performance and reliability, particularly in managing short channel effects and current control in multi-gate transistors.
Innovation Solution
The semiconductor device incorporates a lower pattern on a substrate with a source/drain pattern and an epitaxial insulating liner extending along the sidewall of the semiconductor liner film, which includes a first portion with a specific height and width configuration, and a field insulating film covering the sidewall, to enhance channel control and reduce short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistor is used for scaling, then device density is improved, but short channel effects become more severe
Solution Approach 1:
The patent transitions from planar 2D channel to three-dimensional multi-channel structure (fin or nanowire) where the gate wraps around the channel in multiple dimensions. This dimensional change provides superior electrostatic control over the channel, enabling effective suppression of short channel effects while maintaining high device density through vertical stacking and multi-fold gate coverage.
Solution Approach 2:
The gate structure is nested around the multi-channel active pattern in a wrap-around configuration, with the gate electrode surrounding the fin or nanowire channel from multiple sides. This nested arrangement ensures that the gate electric field penetrates deeply into the channel region, providing enhanced control over carrier flow and suppressing drain-induced barrier lowering effects.
2Reliability
If gate length is increased to improve current control, then current control ability is improved, but device scaling is limited
Solution Approach 1:
The patent achieves superior current control not by increasing gate length in one dimension, but by utilizing three-dimensional gate wrapping around the channel. The multi-fold gate coverage (e.g., tri-gate, multi-gate) provides enhanced electrostatic control equivalent to much longer gates, while maintaining short channel lengths for continued scaling. The vertical and lateral gate extensions work together to control the channel without requiring increased horizontal gate length.
Data Source
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AI summary
A semiconductor device includes a lower pattern (BP1) on a substrate (100) and protruding in a first direction (D1), a source/drain pattern (150) on the lower pattern (BP1) and including a semiconductor liner film (151) in contact with the lower pattern (BP1), and an epitaxial insulating liner (150SP) extending along at least a portion of a sidewall (150SW) of the semiconductor liner film (151), wherein the epitaxial insulating liner (150SP) is in contact with the semiconductor liner film (151), wherein the semiconductor liner film (151) includes a first portion (151_HP1), wherein the first portion of the semiconductor liner film (151) includes a first point (P1) spaced apart from the lower pattern (BP1) at a first height (H11), and a second point (P2) spaced apart from the lower pattern (BP1) at a second height (H12), wherein the second height is greater than the first height, wherein a width of the semiconductor liner film (151) in a second direction (D2) at the first point (P1) is less than a width of the semiconductor liner film (151) in the second direction at the second point (P2), and wherein the epitaxial insulating liner (150SP) extends along at least a portion of a sidewall of the first portion (151_HP1) of the semiconductor liner film (151).