3D Stacked FET PN Junction Isolation for Source/Drain Separation
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Solution Overview
Problem
The manufacturing of 3D stacked field-effect transistor (3DSFET) devices is challenging due to the high device density requiring high aspect-ratio patterning and isolation, particularly in forming dielectric layers that can prevent short circuits between lower and upper source/drain regions while ensuring proper growth of epitaxial structures.
Innovation Solution
A PN junction structure is formed using semiconductor layers of opposite polarity types to electrically isolate the upper source/drain region from the lower source/drain region, replacing the traditional dielectric layer, which simplifies the manufacturing process by eliminating the need for etch-back operations and ensures effective isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dielectric layer is used to electrically isolate the lower source/drain region and the upper source/drain region, then electrical isolation is achieved, but the manufacturing process becomes complex requiring etch-back operations and precise thickness control
Solution Approach 1:
The patent removes the dielectric layer from the isolation structure, replacing it with a PN junction structure formed by semiconductor layers. This extraction of the dielectric layer eliminates the need for etch-back operations and simplifies the manufacturing process while maintaining electrical isolation through the semiconductor-based PN junction structure
Solution Approach 2:
The patent changes the material parameter from dielectric material to semiconductor material with opposite polarity types. By forming a PN junction structure using n-type and p-type semiconductor layers, the isolation mechanism transitions from dielectric barrier to junction-based electrical isolation, fundamentally changing the material parameter to resolve the contradiction
2Reliability
If a dielectric layer is formed to prevent short circuits between lower and upper source/drain regions, then electrical isolation is provided, but epitaxial structure growth becomes difficult due to aspect-ratio constraints
Solution Approach 1:
The patent performs preliminary action by forming the semiconductor layers with opposite polarity types before the epitaxial growth of source/drain regions. The PN junction structure is prepared in advance as the isolation mechanism, allowing subsequent epitaxial growth to proceed without the aspect-ratio constraints that would be imposed by a dielectric layer requiring etch-back operations
Solution Approach 2:
The patent changes the isolation structure from dielectric-based to semiconductor-based, which fundamentally alters the growth characteristics. The semiconductor layers can be grown epitaxially in a continuous manner without the need for etch-back operations, thereby improving ease of manufacture while maintaining short circuit prevention
3Reliability
If traditional dielectric layer isolation is used, then electrical isolation between stacked transistors is achieved, but the manufacturing process requires high aspect-ratio patterning and multiple steps
Solution Approach 1:
The patent merges the isolation structure formation with the semiconductor layer formation process. By integrating the PN junction structure creation into the existing semiconductor fabrication flow, the patent eliminates separate dielectric layer deposition and etch-back operations, thereby improving manufacturing efficiency and productivity
Solution Approach 2:
The patent extracts the dielectric layer from the manufacturing process entirely, replacing it with a semiconductor-based PN junction structure. This removal of the dielectric layer eliminates multiple manufacturing steps including deposition, patterning, and etch-back operations, significantly improving productivity while maintaining electrical isolation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The PN junction structure effectively prevents current flow between the lower and upper source/drain regions, functioning as a reliable electrical isolation structure, thus simplifying the manufacturing process and enhancing the reliability of 3DSFET devices.
Implementation Method 1
a PN junction structure, between the lower source/drain region and the upper source/drain region, configured to electrically isolate the upper source/drain region from the lower source/drain region
Implementation Method 2
growing a lower epitaxial structure (Epi) of a 1st polarity type based on the lower channel structure
Data Source
AI summary
Provided is a three-dimensionally stacked field-effect transistor (3DSFET) device which includes: a lower source/drain region of a 1st polarity type connected to a lower channel structure; an upper source/drain region of a 2nd polarity type, connected to an upper channel structure, above the lower source/drain region; and a PN junction structure, between the lower source/drain region and the upper source/drain region, configured to electrically isolate the upper source/drain region from the lower source/drain region, wherein the PN junction structure includes a 1st region of the 1st polarity type and a 2nd region of the 2nd polarity type.