3D DRAM Gate Structure Formation Using a Virtual Connecting Layer
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Solution Overview
Problem
The existing 3D DRAM technology faces complexity in forming a gate metal layer that connects adjacent transistors in the same layer, as the gate structures of two adjacent transistors cannot be formed simultaneously, leading to a complicated preparation process.
Innovation Solution
A method involving ion implantation to form an active virtual connecting layer that extends in a specific direction and is partially located in isolation trenches, facilitating the formation of a gate structure and serving as an electron barrier to isolate adjacent gate structures, thereby simplifying the process and reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a gate metal layer is formed to connect gate structures of adjacent transistors in the same layer, then the gate structures can be led out by a same gate metal layer (word line), but the gate metal layer cannot be formed at the same time as other gate structures, leading to complex preparation process
Solution Approach 1:
The patent applies preliminary action by forming the virtual connecting layer in advance during the stack structure formation process, before the gate structures are created. This virtual connecting layer is positioned in the isolation trenches and will later serve as the foundation for the gate metal layer, eliminating the need for separate formation steps and simplifying the overall preparation process.
Solution Approach 2:
The patent introduces a virtual connecting layer as an intermediary element that bridges the isolation trenches and enables subsequent gate structure formation. This intermediary layer acts as a mediator that facilitates the connection of gate structures across adjacent transistors, allowing the gate metal layer to be formed simultaneously with other gate structures without increasing process complexity.
2Reliability
If isolation trenches are used to separate stack structures, then adjacent gate structures are isolated, but the gate structures cannot be connected simultaneously, increasing process complexity
Solution Approach 1:
The patent applies multi-functionality by making the virtual connecting layer serve dual purposes: it provides electrical connection between adjacent gate structures while simultaneously maintaining the isolation function in the trenches. This single element performs both connection and isolation tasks, eliminating the need for separate structures and reducing overall process complexity while preserving reliable gate structure isolation.
3Manufacturing precision
If multiple preparation steps are used to form gate structures and connecting layers separately, then each structure can be optimized, but the overall process becomes complex and time-consuming
Solution Approach 1:
The patent merges the formation of the connecting layer with the gate structure fabrication process. The virtual connecting layer is formed simultaneously with the gate structures in the same processing steps, eliminating separate preparation stages. This consolidation maintains manufacturing precision for both the connecting layer and gate structures while significantly improving fabrication efficiency by reducing the total number of process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the formation of a gate metal layer connecting gate structures in the same layer, reduces manufacturing costs, and improves the yield of semiconductor structures by minimizing leakage current through the use of a virtual connecting layer as an electron barrier.
Implementation Method 1
Ion implantation is performed on sidewalls of the stack structure in the first direction, so as to form an active virtual connecting layer extending in the first direction and partially located in the isolation trenches
Data Source
AI summary
A method for forming a semiconductor structure is provided. The method includes: providing a base, the base including a first area and second areas located outside the first area, the first area including stack structures and isolation trenches alternately arranged in a first direction, the first direction being any direction in a plane where the base is located; performing ion implantation on sidewalls of the stack structure in the first direction, so as to form an active virtual connecting layer extending in the first direction and partially located in the isolation trenches; and forming a gate structure on a surface of the active virtual connecting layer.