Nanosheet Channel Layout With Interbridge Regions for Higher On-Current
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Solution Overview
Problem
As the scale of fin width in fin field effect transistors (FinFETs) decreases, channel width variations lead to mobility loss, prompting the exploration of nano-FETs with gate encasement for improved electrostatic control and reduced leakage currents, but these devices face challenges in enhancing on-current efficiency.
Innovation Solution
The introduction of interbridge channels localized to the periphery regions of nanostructure channels in nano-FETs, which reduces concave corners and enhances gate control, leading to increased on-current and electron density, as demonstrated through simulation results showing improved on-current, sub-threshold swing, and on-current/off-current ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the scale of fin width in FinFETs is decreased to improve integration density, then more components can be integrated into a given area, but channel width variations lead to mobility loss
Solution Approach 1:
The patent transitions from planar FinFET channel structures to three-dimensional nanosheet channel structures with interbridge channels. This dimensional change allows the channel to extend vertically and laterally, improving electrostatic control and reducing mobility loss while maintaining small footprint for high integration density.
Solution Approach 2:
The patent implements nested channel structures where interbridge channels are positioned between nanosheet channels, creating a multi-level nested configuration. This nesting approach maximizes the use of available space, improves gate control over the channel regions, and maintains compact device dimensions for high-density integration.
2Reliability
If nano-FETs with gate encasement are used to improve electrostatic control and reduce leakage currents, then leakage is reduced, but on-current efficiency is compromised
Solution Approach 1:
The patent segments the channel into multiple discrete nanosheet channels with interbridge channels connecting them. This segmentation allows the gate to encase and control each segment independently, reducing leakage through improved electrostatic control while the combined segments provide sufficient total channel width for high on-current efficiency.
Solution Approach 2:
The patent applies different channel configurations locally - nanosheet channels in certain regions and interbridge channels in other regions - to optimize performance. This local quality approach allows tailored electrostatic control and current flow paths that simultaneously reduce leakage and enhance on-current efficiency.
Data Source
AI summary
A device comprises source/drain regions over a substrate and spaced apart along a first direction, a first gate structure between the source/drain regions, and a first channel structure surrounded by the first gate structure. The first channel structure comprises alternately stacking first semiconductor layers and second semiconductor layers. When viewed in a cross section taken along a second direction perpendicular to the first direction, central axes of the second semiconductor layers are laterally offset from central axes of the first semiconductor layers.