Gate-Top Dielectric Cap for Low-Capacitance Self-Aligned Contacts
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Solution Overview
Problem
Existing self-aligned contact formation processes for multi-gate transistors face challenges such as high parasitic capacitance and electrical shorts due to the use of high-k dielectric materials and the breaching of gate spacer layers during the formation of source/drain contact openings.
Innovation Solution
The use of a dielectric material with a dielectric constant between 3.9 and 10 for the capping dielectric layer, which balances etch resistance and parasitic capacitance, and the formation of rounded top surfaces of the high-k metal gate structure, gate spacers, and contact etch stop layer to ensure coplanarity and prevent electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If high-k dielectric material is used for the capping dielectric layer, then etch resistance is improved, but parasitic capacitance increases
Solution Approach 1:
The patent applies parameter changes by selecting a dielectric material with a specific dielectric constant range (3.9 to 10) for the capping dielectric layer. This parameter optimization balances etch resistance requirements with parasitic capacitance reduction, resolving the contradiction between using high-k material for etch protection and minimizing capacitance for device performance.
2Ease of manufacture
If the recess is defined in gate spacer layers, then self-aligned contact formation is enabled, but electrical shorts occur during source/drain contact opening formation
Solution Approach 1:
The patent introduces an intermediary protective layer configuration where the gate spacer layer is positioned to extend beyond the gate structure sidewalls, creating a protective overhang that prevents etch breaching during source/drain contact formation. This intermediary structure enables self-aligned contact formation while simultaneously preventing electrical shorts.
3Productivity
If geometry size is decreased to increase functional density, then production efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-forming the gate spacer layer to extend beyond the gate structure sidewalls before source/drain contact formation. This preliminary configuration of the spacer layer creates built-in alignment and protection features that simplify subsequent manufacturing steps, enabling scaled geometry processing without proportionally increasing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance and increases yield by providing a balanced etch resistance and minimizing electrical shorts, thereby improving the reliability of self-aligned contact structures in multi-gate transistors.
Implementation Method 1
The dielectric cap includes a dielectric constant between about 3.9 and about 10
Data Source
AI summary
Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to the present disclosure includes an active region having a channel region and a source/drain region, a gate structure over the channel region, a gate spacer layer disposed over the channel region and extending along a sidewall of the gate structure, an epitaxial source/drain feature over the source/drain region, a contact etch stop layer (CESL) disposed on the epitaxial source/drain feature and extending along a sidewall of the gate spacer layer, a source/drain contact disposed over the epitaxial source/drain feature, and a dielectric cap layer disposed over the gate structure, the gate spacer layer and at least a portion of the CESL. A sidewall of the source/drain contact is in direct contact with a sidewall of the CESL.