FinFET SiGe Source/Drain Buffer Structure for Low Resistance
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Solution Overview
Problem
As IC devices downscale, ensuring high operating speed and accuracy while improving the performance and reliability of fin-type field-effect transistors (FETs) with increased integration density and reduced sizes is a challenge.
Innovation Solution
The integration of a fin-type active region with a gate line surrounding a channel region, where the source/drain region includes sequentially stacked layers of Si1-xGex with different germanium concentrations, and a conformal buffer layer to reduce resistance and growth defects, enhancing electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of IC devices is reduced and integration density is increased, then miniaturization is achieved, but the performance and reliability of fin-type FETs deteriorate
Solution Approach 1:
The source/drain region is divided into multiple layers with different Ge concentrations (first buffer layer with lower Ge concentration, second buffer layer with intermediate Ge concentration, and main body layer with higher Ge concentration). This gradient structure provides local quality variation to reduce misfit dislocation and improve FET reliability while maintaining miniaturization.
Solution Approach 2:
The source/drain region employs a composite structure consisting of SiGe layers with different Ge concentrations stacked sequentially. This composite material approach allows optimization of both mechanical stress management and electrical performance, resolving the contradiction between device miniaturization and FET reliability.
2Volume of moving object
If the size of IC devices is reduced and integration density is increased, then miniaturization is achieved, but the performance of fin-type FETs deteriorates
Solution Approach 1:
The gradient Ge concentration structure in the source/drain region creates local quality variation that reduces misfit dislocation and improves carrier mobility. This enhances FET performance (current drive capability) while maintaining the miniaturized device structure.
Solution Approach 2:
The Ge concentration parameter is varied across different layers (first buffer layer: lower Ge concentration, second buffer layer: intermediate Ge concentration, main body layer: higher Ge concentration). This parameter change optimizes the balance between lattice matching and stress control, improving FET performance in miniaturized devices.
3Device complexity
If a single-layer source/drain structure is used, then the structure is simple, but resistance is high and electrical performance is poor
Solution Approach 1:
The source/drain region is segmented into three distinct layers (first buffer layer, second buffer layer, and main body layer) with different Ge concentrations. This segmentation reduces misfit dislocation and optimizes electrical performance, achieving low resistance while maintaining manageable structural complexity through systematic layering.
Solution Approach 2:
The multi-layer SiGe structure functions as a composite material system where each layer contributes specific properties. The gradient Ge concentration composition optimizes both mechanical stress distribution and electrical conductivity, reducing source/drain resistance and improving overall electrical performance.
Data Source
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AI summary
An integrated circuit (IC) device includes a fin-type active region, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region, a source/drain region that is adjacent to the gate line on the fin-type active region and has a sidewall facing the channel region, wherein the source/drain region includes a first buffer layer, a second buffer layer, and a main body layer, which are sequentially stacked in a direction away from the fin-type active region, each include a Si1-xGex layer (x ≠ 0) doped with a p-type dopant, and have different Ge concentrations, and the second buffer layer conformally covers a surface of the first buffer layer that faces the main body layer. A thickness ratio of the side buffer portion to the bottom buffer portion is in a range of about 0.9 to about 1.1.