Stacked CFET Source/Drain Notch Isolation for Short-Circuit Prevention
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Solution Overview
Problem
In advanced semiconductor technology nodes beyond 5 nm, growing independently stacked nFET and pFET source/drain epitaxy while maintaining vertical integration and electrical disconnection is challenging due to superposed n-doped and p-doped epitaxy, leading to device shorting and reliability issues.
Innovation Solution
The formation of recessed notches in the upper surface of the lower source/drain regions of stacked complementary field effect transistors (CFETs) beneath an isolation layer enhances physical separation, allowing for the deposition of isolating dielectric materials between the upper and lower source/drain regions, ensuring electrical disconnection and preventing short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If independently stacked nFET and pFET source/drain epitaxy are grown, then vertical integration is achieved, but electrical disconnection becomes difficult to maintain due to superposed doping
Solution Approach 1:
The source/drain region is segmented into two distinct levels: a lower source/drain region and an upper source/drain region. The lower region is recessed to create a notch, physically separating it from the upper region. This segmentation allows independent epitaxial growth of n-doped and p-doped regions without electrical interference, maintaining both vertical integration and electrical disconnection.
Solution Approach 2:
The solution transitions from a planar two-dimensional layout to a three-dimensional stacked structure. By growing source/drain regions at different vertical levels (z-dimension) rather than adjacent horizontal positions, the patent achieves vertical integration while the recessed notch ensures electrical isolation between the stacked regions.
2Ease of manufacture
If superposed n-doped and p-doped epitaxy are grown, then device fabrication is simplified, but device shorting and reliability issues occur
Solution Approach 1:
The epitaxial growth process is segmented into separate stages for lower and upper source/drain regions. The lower region is formed first with a recessed notch, then the upper region is grown independently. This segmentation prevents superposed doping while maintaining ease of manufacture through sequential epitaxial processes.
Solution Approach 2:
The recessed notch is formed in the lower source/drain region before growing the upper source/drain region. This preliminary action creates a physical barrier that prevents electrical shorting between the subsequently grown upper region, ensuring reliability from the outset of the fabrication process.
3Reliability
If physical separation between source/drain regions is enhanced, then electrical disconnection is improved, but device area increases
Solution Approach 1:
Instead of increasing horizontal separation distance, the patent utilizes the vertical dimension by stacking source/drain regions at different levels. The recessed notch provides electrical isolation without requiring additional lateral space, thus maintaining compact device footprint while achieving enhanced electrical disconnection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of vertically integrated, electrically isolated CFET structures with enhanced physical separation, improving device reliability and preventing short circuits, thus addressing the complexities of scaling in advanced semiconductor nodes.
Implementation Method 1
forming an isolation layer in the notch and above the bottom source/drain region
Data Source
AI summary
A complementary field effect transistor (CFET) structure including a first transistor disposed above a second transistor, and a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, wherein the second source/drain region comprises a recessed notch beneath the first source/drain region.