Multi-Gate IC Structure for Short-Channel Leakage Control
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Solution Overview
Problem
As integrated circuits are downscaled, they experience a reliability decrease due to the short channel effect, which is not effectively addressed by existing technologies, prompting the need for improved multi-gate structure transistors.
Innovation Solution
The proposed integrated circuit design includes a substrate with a fin active region, semiconductor patterns, a gate electrode with a main gate part and sub gate parts, a spacer structure, and a source/drain region, where the uppermost semiconductor pattern has a specific width profile and the main gate part has a sloped sidewall, enhancing the spacing between the source/drain region and the gate electrode to reduce leakage current and prevent process defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integrated circuits are downscaled to increase integration density, then productivity and integration level are improved, but reliability deteriorates due to short channel effect
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional multi-gate structures (FinFET, nanosheet, nanowire). By adding vertical dimension and creating multiple gates that wrap around the channel, the design achieves better electrostatic control without further reducing horizontal feature sizes, thus maintaining reliability while continuing downsaling for higher integration density.
Solution Approach 2:
The multi-gate structure implements nested configuration where inner gates are positioned within or around the channel region, with outer gates surrounding them. This nested arrangement maximizes the gate-controlled surface area of the channel, providing superior electrostatic control that counteracts short channel effects even as device dimensions are reduced for higher integration.
2Reliability
If multi-gate structure transistors are implemented to reduce short channel effect, then reliability is improved, but device complexity increases
Solution Approach 1:
The gate structure is segmented into multiple independent gates (inner gate and outer gate) that can be separately formed and controlled. This segmentation allows each gate to independently control different portions of the channel, providing flexible electrostatic control while enabling modular manufacturing processes that can be integrated into existing fabrication workflows.
Solution Approach 2:
The multi-gate structure serves multiple functions: the inner gate provides primary channel control while the outer gate enhances electrostatic control and can independently modulate device characteristics. This multi-functionality allows a single device structure to address short channel effects while providing additional control knobs for optimizing performance, reducing leakage, and enabling novel device modes without requiring entirely different transistor architectures.
3Reliability
If spacing between source/drain region and gate electrode is increased to reduce leakage current, then reliability is improved, but area occupied by device increases
Solution Approach 1:
Instead of increasing horizontal spacing between source/drain and gate, the patent utilizes vertical spacing and three-dimensional gate wrapping. The multi-gate structure extends vertically around the channel, providing leakage control in the vertical dimension while maintaining compact horizontal footprints. This allows sufficient separation between charged regions without expanding the planar device area.
Solution Approach 2:
The spacer structure acts as an intermediary element positioned between the source/drain region and the gate electrode. This spacer provides physical separation and electrical isolation, reducing direct leakage paths while occupying minimal space. The spacer enables controlled distance maintenance without requiring large area expansions, effectively mediating the interaction between conductive regions.
Data Source
AI summary
An integrated circuit includes a fin active region protruding from a substrate, a plurality of semiconductor patterns on an upper surface of the fin active region, a gate electrode that surrounds the plurality of semiconductor patterns and includes a main gate part on an uppermost one of the plurality of semiconductor patterns and sub gate parts between the plurality of semiconductor patterns, a spacer structure on a sidewall of the main gate part, and a source/drain region at a side of the gate electrode. The source/drain region is connected to the plurality of semiconductor patterns and contacts a bottom surface of the spacer structure. A top portion of the uppermost semiconductor pattern has a first width. A bottom portion of the uppermost semiconductor pattern has a second width smaller than the first width.