SOI Substrate Bonding With Charge Traps for Lower PSC Loss

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Solution Overview

Problem

Integrated circuits on bulk semiconductor substrates face issues with parasitic surface conduction (PSC) leading to substrate loss and harmonic distortion due to parasitic capacitance, which are not adequately addressed by traditional silicon on insulator (SOI) devices.

Innovation Solution

A silicon on insulator (SOI) device is developed with a trap-rich layer having nano-dots or a doped negative charge layer positioned next to an induced positive fixed charge layer, which traps negative carriers to neutralize positive charges, thereby interrupting PSC channels and increasing substrate resistivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If traditional bulk semiconductor substrates are used, then device fabrication is simple, but parasitic surface conduction causes substrate loss and harmonic distortion

Engineering Contradiction:

Improvefabrication simplicityVSAvoidparasitic surface conduction

Core Design Contradiction:

Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The substrate is segmented into multiple functional layers: handle substrate, buried oxide layer, trap-rich layer with nano-dots, and device layer. This segmentation isolates the active devices from the bulk substrate, eliminating parasitic surface conduction while maintaining fabrication feasibility through standard SOI processes

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A trap-rich layer containing nano-dots is introduced as an intermediary between the buried oxide layer and the device layer. This intermediate layer acts as a charge trap that neutralizes positive charges at the oxide-substrate interface, thereby eliminating parasitic surface conduction channels without requiring complete substrate removal

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If SOI substrate with thin active layer is used, then parasitic capacitance decreases and power-speed performance improves, but positive fixed charge layers cause parasitic surface conduction

Engineering Contradiction:

Improvepower-speed performanceVSAvoidparasitic surface conduction from positive charges

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The positive fixed charges at the oxide interface, which normally cause parasitic surface conduction, are converted into a beneficial structure by introducing a trap-rich layer that deliberately traps negative carriers. This transforms the harmful charge accumulation into a controlled charge compensation mechanism that eliminates PSC while maintaining the low parasitic capacitance benefits of thin SOI structures

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The electrical parameters at the oxide interface are changed by introducing a layer with high trap density. This changes the charge distribution profile from a simple positive fixed charge layer to a compensated structure where trapped negative carriers neutralize the positive charges, thereby changing the interface electrical characteristics to eliminate parasitic conduction

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces parasitic surface conduction, increases effective resistivity, and minimizes substrate loss and harmonic distortion by neutralizing positive charges in the induced positive fixed charge layer.

Implementation Method 1

a trap-rich layer having nano-dots and an oxide layer are stacked on a high resistivity substrate sequentially... trap-rich layer having nano-dots is applied to trap negative carriers and wipe out induced positive charges

Methodology Applied

Scientific EffectCharge trapping: Absorption (physical)

Implementation Method 2

a doped negative charge layer including negative carriers therein is applied instead, to wipe out the positive charges

Methodology Applied

Scientific EffectCharge carrier injection: Ion Implantation

Implementation Method 3

the oxide layer is bonded with the buried oxide layer

Methodology Applied

Scientific EffectBonding: Chemical Bonding

Data Source

PatentUS11888025B2Silicon on insulator (SOI) device and forming method thereof

Publication Date: 2024.01.30 UNITED MICROELECTRONICS CORP

AI summary

A silicon on insulator (SOI) device includes a wafer and a trap-rich layer. The wafer includes a top silicon layer disposed on a buried oxide layer. The trap-rich layer having nano-dots and an oxide layer are stacked on a high resistivity substrate sequentially, wherein the oxide layer is bonded with the buried oxide layer. Or, a silicon on insulator (SOI) device includes a wafer and a high resistivity substrate. The wafer includes a top silicon layer disposed on a buried oxide layer. The high resistivity substrate is bonded with the buried oxide layer, wherein a positive fixed charge layer is induced at a surface of the buried oxide layer contacting the high resistivity substrate, and a doped negative charge layer is right next to the positive fixed charge layer. The present invention also provides a method of forming said silicon on insulator (SOI) device.