GAA Source/Drain Plug Layout for Lower Parasitic Resistance

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Solution Overview

Problem

Gate-all-around transistors face challenges in enhancing performance due to low channel current values, particularly in channel layers farther away from the source/drain plug, where high parasitic resistance and voltage drops hinder increased drive current and device efficiency.

Innovation Solution

The semiconductor structure includes source/drain plugs that contact the top of the source/drain structures and extend to longitudinal side walls, allowing direct current flow through side walls of the source/drain doped layers, reducing parasitic resistance and increasing channel current values by using materials with lower resistivity than the source/drain structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If source/drain plugs are only contacted at the top of source/drain structures, then manufacturing is simpler, but parasitic resistance is high and channel current is low

Engineering Contradiction:
Improvechannel currentVSAvoidsource/drain plug contact structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The source/drain plug contact structure transitions from a single-point top contact to a multi-dimensional contact system. The plug contacts the source/drain structure at the top surface and extends laterally to contact the channel structure at the sides, creating a three-dimensional contact network that reduces parasitic resistance through multiple current pathways.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The source/drain plug is positioned within the source/drain structure and extends to nest against the channel structure. This nested configuration allows the plug to be embedded in the source/drain structure while simultaneously contacting the channel structure, maximizing electrical contact area and minimizing resistance.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Productivity

If channel layers are extended farther from the base, then device integration is improved, but parasitic resistance increases and drive current decreases

Engineering Contradiction:
Improvedevice integrationVSAvoiddrive current
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The source/drain plug acts as an intermediary conductive element between the source/drain structure and the channel structure. By positioning the plug to contact both structures, it provides a low-resistance electrical pathway that mediates the connection, allowing current to flow efficiently from the source/drain structure to the channel structure even when the channel layers are extended.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The source/drain plug provides localized high-conductivity regions at critical contact points between the source/drain structure and channel structure. This local enhancement of electrical quality compensates for the increased parasitic resistance that would otherwise result from extending the channel layers farther from the base.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration significantly enhances the drive current and optimizes the performance of the semiconductor structure by reducing voltage drops and increasing channel current values, especially in channel layers closer to the base.

Implementation Method 1

the source/drain plug is further in contact with at least one of a longitudinal side wall facing away from the gate structure, a side wall along a horizontal first side, and a side wall along a horizontal second side of the first source/drain doped layer

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS20230411469A1Semiconductor structure and formation method thereof
Publication Date: 2023.12.21 SEMICON TECH INNOVATION CENT(BEIJING) CORP
  • US20230411469A1 patent drawing
  • US20230411469A1 patent drawing
  • US20230411469A1 patent drawing

AI summary

A semiconductor structure and a formation method thereof are provided. The structure includes: a channel structure layer, where the channel structure layer includes a plurality of first channel layers sequentially spaced apart from bottom to top, the first channel layers extend along a horizontal direction; gate structures stretching across the channel structure layer and surrounding the first channel layers; source/drain structures located on two sides of the gate structure, where the source/drain structure includes a first source/drain doped layer located on a side wall of the first channel layer; and source/drain plugs in contact with tops of the source/drain structures, where the source/drain plug is further in contact with at least one of a longitudinal side wall facing away from the gate structure, a side wall along a horizontal first side, and a side wall along a horizontal second side of the first source/drain doped layer.