Core-Shell TFET Structure for Low-Leakage High On-State Current
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Solution Overview
Problem
As semiconductor devices shrink, challenges such as increased current leakage, signal crossovers, and power consumption become significant, with existing tunneling field-effect transistors (TFETs) not fully addressing these issues, particularly in achieving low power consumption and high on-state current.
Innovation Solution
The implementation of a semiconductor device structure with a core channel region, a barrier layer, and a shell, where the conduction energy band of the shell is aligned with the conduction energy band of the barrier layer, utilizing a dual-gate stack and doping to modulate the energy bands, enhancing on-state current while minimizing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional MOS field-effect transistors are used, then device scaling is achieved, but current leakage increases and power consumption rises
Solution Approach 1:
The patent changes the fundamental operating parameter of the transistor by switching from conventional MOSFET operation to tunneling FET operation, utilizing band-to-band tunneling mechanism. This parameter change enables sub-60 mV/dec subthreshold swing, which directly addresses the current leakage issue while maintaining device scaling capability
Solution Approach 2:
The patent employs composite material structures including heterojunctions (e.g., InAs/GaAs, InSb/InAlAs) to create the tunneling FET. These composite materials enable the tunneling effect while controlling off-state leakage, resolving the contradiction between scaling and leakage reduction
2Area of stationary object
If feature size is reduced to increase device density, then more devices per unit area are achieved, but current leakage becomes more noticeable
Solution Approach 1:
The patent changes the subthreshold swing parameter to sub-60 mV/dec through tunneling mechanism, which allows the transistor to maintain low off-state current even as feature sizes are reduced. This parameter change decouples the relationship between device density and current leakage
Solution Approach 2:
The patent introduces a new dimensional approach by utilizing the energy band structure dimension (conduction band alignment) rather than solely relying on physical dimension scaling. The conduction energy band alignment between shell and barrier layer creates a tunneling pathway that is independent of lateral feature size, enabling high density without proportional increase in leakage
3Loss of energy
If tunneling FET structure is implemented, then off-state leakage is reduced, but on-state current is insufficient
Solution Approach 1:
The patent applies local quality by creating distinct regions with different properties: the shell region provides high-quality conduction channels for high on-state current, while the barrier layer provides high-quality blocking for low off-state leakage. This spatial differentiation of functional quality resolves the contradiction between on and off state performance
Solution Approach 2:
The patent uses composite material heterostructures where different semiconductor materials (e.g., InAs, GaAs, InSb, InAlAs) are combined to create regions with optimized properties. The shell material is selected for high carrier mobility to maximize on-state current, while the barrier layer material is selected for appropriate band alignment to minimize off-state leakage
4Use of energy by stationary object
If power supply voltage is reduced, then power consumption decreases, but achieving high on-state current becomes difficult
Solution Approach 1:
The patent changes the voltage-parameter relationship by achieving sub-60 mV/dec subthreshold swing through tunneling mechanism. This allows the transistor to reach high on-state current at lower voltage thresholds, decoupling the traditional linear relationship between supply voltage and on-state current
Solution Approach 2:
The tunneling FET structure provides multi-functionality by simultaneously achieving low voltage operation, high on-state current, and low off-state leakage in a single device architecture, eliminating the need to trade off between these parameters
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases on-state current with low power consumption and reduces leakage current, enabling high-performance CMOS speed at reduced voltage, such as 0.3V, by aligning energy bands and providing electrostatic modulation.
Implementation Method 1
the conduction energy band of the shell is aligned with the conduction energy band of the barrier layer
Implementation Method 2
utilizing a dual-gate stack and doping to modulate the energy bands, enhancing on-state current while minimizing leakage
Data Source
AI summary
A semiconductor device includes first and second source/drain regions, a core channel region, a barrier layer, a shell, and a gate stack. The core channel region is between the first and second source/drain regions and is doped with first dopants. The barrier layer is between the core channel region and the second source/drain region and is doped with second dopants. The shell is over the core channel region and the barrier layer. The gate stack is over the shell.