Multi-Layer Inner Spacers for Low-Capacitance GAA Transistors
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Solution Overview
Problem
Conventional GAA transistors with inner spacers face challenges in defect induction during etch back processes, leading to issues like gate spacer damage, hard mask loss, and shallow-trench isolation loss, which prevent the use of low-k dielectric materials and increase parasitic capacitance.
Innovation Solution
A multi-layer inner spacer feature is introduced, comprising a first inner spacer as an etch stop layer and a second inner spacer made of low-k dielectric material, optionally with a third spacer, to mitigate defects and reduce parasitic capacitance during the formation of source/drain features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional single-layer inner spacers are used in GAA transistors, then the fabrication process is simpler, but defects are induced during etch back processes including gate spacer damage, hard mask loss, and shallow-trench isolation loss
Solution Approach 1:
The inner spacer is divided into multiple layers: a first inner spacer layer made of a first dielectric material and a second inner spacer layer made of a second dielectric material with different etch selectivity. This segmentation allows the etch back process to selectively remove sacrificial material without damaging the inner spacer or surrounding structures, thereby resolving the contradiction between manufacturing simplicity and defect reduction.
Solution Approach 2:
The multi-layer inner spacer structure acts as an intermediary protective barrier during the etch back process. The first dielectric material layer protects the gate spacer and hard mask, while the second dielectric material layer with different etch selectivity enables selective removal of sacrificial material. This intermediary structure prevents direct contact between the etchant and sensitive components, eliminating defects while maintaining process feasibility.
2Device complexity
If conventional inner spacers are used in GAA transistors, then the device structure is simpler, but parasitic capacitance between gate structures and source/drain features increases
Solution Approach 1:
The patent changes the dielectric material parameters of the inner spacer by using two different dielectric materials with different etch selectivity and different dielectric properties. The second inner spacer layer, made of a dielectric material with lower parasitic capacitance characteristics, directly reduces the harmful capacitive coupling between gate structures and source/drain features while the first layer provides structural integrity and protection.
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a first semiconductor channel member and a second semiconductor channel member extending between the first and second source/drain features, and a first dielectric feature and a second dielectric feature each including a first dielectric layer and a second dielectric layer different from the first dielectric layer. The first and second dielectric features are sandwiched between the first and second semiconductor channel members.