Stacked MOSFET Gate Structure With Silicon Oxide Diffusion Barriers
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, requiring improved reliability and electric characteristics.
Innovation Solution
A semiconductor device with vertically stacked semiconductor patterns, source/drain patterns, and gate electrodes, where barrier patterns comprising epitaxial single-crystalline silicon oxide are used to enhance reliability and efficiency, with specific oxygen concentration and thickness ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for smaller pattern size, then device density and integration are improved, but operational properties and reliability deteriorate
Solution Approach 1:
The patent transitions from planar MOS-FET structures to vertically stacked three-dimensional structures. Multiple semiconductor patterns are stacked vertically to form channel regions, enabling continued scaling and increased device density while maintaining operational reliability through the three-dimensional architecture that provides better gate control and electrical characteristics
Solution Approach 2:
Barrier patterns composed of single-crystalline silicon oxide are introduced as intermediary layers between adjacent semiconductor patterns and between semiconductor patterns and gate electrode portions. These barrier patterns prevent harmful interactions such as dopant diffusion and electrical interference, thereby maintaining reliability in the scaled-down vertical structure
2Reliability
If barrier patterns with single-crystalline silicon oxide are used between semiconductor patterns and gate electrode portions, then reliability and electric characteristics are improved, but device complexity increases
Solution Approach 1:
The patent specifies precise parameters for the barrier patterns including oxygen concentration ranges (7.0E18 to 1.3E19 atoms/cm³) and thickness ranges (30 Å to 40 Å). By controlling these parameters within specific ranges, the barrier patterns achieve optimal performance in preventing dopant diffusion and electrical interference while maintaining manufacturability and avoiding excessive complexity
3Productivity
If vertically stacked semiconductor patterns are implemented, then device density and performance are improved, but manufacturing precision requirements increase
Solution Approach 1:
The barrier patterns are formed as preliminary structures before the gate electrode portions are deposited. This preliminary formation of barrier patterns with controlled thickness and position provides a foundation that guides subsequent manufacturing steps, ensuring proper alignment of the vertically stacked structures and reducing the precision requirements for later alignment-critical steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the reliability and electric characteristics of semiconductor devices by preventing dopant diffusion and enhancing etching selectivity, thereby improving process efficiency and device performance.
Implementation Method 1
barrier patterns which comprise an epitaxial layer including single-crystalline silicon oxide
Data Source
AI summary
A semiconductor device may include a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns, which are vertically stacked to be spaced apart from each other, a source/drain pattern connected to the plurality of semiconductor patterns, a gate electrode including a plurality of gate electrode portions, a gate electrode portion interposed between adjacent ones of the semiconductor patterns, and a plurality of barrier patterns each comprising an epitaxial layer including single-crystalline silicon oxide. ,A barrier pattern interposed between each of the adjacent ones of the semiconductor patterns and a respective gate electrode portion.