Conformal Multi-Silicide Contacts for 3D GAA FET Coverage
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Solution Overview
Problem
In 3D gate-all-around (GAA) FETs, the non-conformal formation of contact silicide layers leads to insufficient coverage and high contact resistance, degrading performance and reducing manufacturing yield due to the use of non-conformal physical vapor deposition processes on complex 3D surfaces.
Innovation Solution
A multi-silicide structure with at least two conformal silicide layers, including a metal-rich and a silicon-rich layer, is formed to increase thickness and ensure conformality, along with a capping layer, to reduce contact resistance, and dynamic adjustment of etch process parameters using an analysis model to enhance etching reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If non-conformal physical vapor deposition is used to form contact silicide, then the formation process is simple, but the coverage is insufficient and contact resistance is high
Solution Approach 1:
The contact silicide structure is divided into multiple layers: a first conformal silicide layer directly on the source/drain, a second conformal silicide layer on the first silicide layer, and an optional third conformal silicide layer on the second silicide layer. Each layer is formed by separate deposition processes to achieve cumulative conformal coverage and reduce contact resistance effectively.
Solution Approach 2:
The patent transitions from a single-layer planar silicide structure to a multi-layer three-dimensional conformal structure. By stacking multiple conformal silicide layers vertically, the invention achieves complete surface coverage on complex 3D surfaces while maintaining low contact resistance through increased effective contact area.
2Manufacturing precision
If single silicide layer is formed, then the structure is simple, but the thickness is insufficient for adequate coverage
Solution Approach 1:
The silicide structure is segmented into multiple discrete layers (first conformal silicide layer, second conformal silicide layer, and optionally third conformal silicide layer), each with specific thickness requirements. This segmentation allows each layer to be optimized independently for coverage while the cumulative effect provides adequate total thickness for reliable electrical contact.
Solution Approach 2:
The patent implements a nested multi-layer silicide structure where the second conformal silicide layer is deposited on the first conformal silicide layer, and optionally a third conformal silicide layer is deposited on the second. This nested arrangement achieves increased effective thickness and coverage while maintaining a organized, manufacturable structure.
3Manufacturing precision
If conventional etch process is used, then the process is straightforward, but the etching reliability is insufficient for precise features
Solution Approach 1:
The etch process parameters are made dynamic rather than static. The system continuously monitors etch characteristics (such as etch rate, uniformity, and anisotropy) and adjusts parameters including gas flow rates, pressure, power, and temperature in real-time to maintain optimal etching conditions throughout the process, ensuring both precision and reliability.
Solution Approach 2:
The etch process incorporates feedback mechanisms where etch characteristics are monitored during processing and the results are fed back to adjust subsequent etch parameters. This closed-loop control ensures that etching precision and reliability are maintained by correcting deviations from target performance in real-time based on actual process measurements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-silicide structure reduces contact resistance and improves the performance and yield of 3D GAA FETs by ensuring adequate coverage and reliability in the etching process, while the dynamic etch process adjustments enhance the manufacturing process's precision and efficiency.
Implementation Method 1
non-conformal physical vapor deposition processes on complex 3D surfaces
Implementation Method 2
dynamic adjustment of etch process parameters using an analysis model to enhance etching reliability
Data Source
AI summary
A semiconductor device includes a multi-silicide structure comprising at least two conformal silicide layers. The multi-silicide structure may include a first conformal silicide layer on a source/drain, a second conformal silicide layer on the first conformal silicide layer, and a capping layer over the second conformal silicide layer. The semiconductor device includes a contact structure on the multi-silicide structure. The semiconductor device includes a dielectric material around the contact structure. In some implementations, a controller may determine etch process parameters to be used by an etch tool to perform an iteration of an atomic layer etch (ALE) process on the semiconductor device.