Inner Spacer Layout in GAA FETs for Source-Drain Gate Isolation
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Solution Overview
Problem
The scaling down of semiconductor devices has increased complexity and parasitic capacitance between source/drain regions and gate structures in FET devices, negatively impacting performance, especially at high frequencies.
Innovation Solution
The introduction of inner spacer structures made of low-k dielectric materials or air-gaps between the source/drain regions and gate structures in FET devices, which reduce capacitive coupling and parasitic capacitance by 20% to 60%.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to increase storage capacity and processing speed, then device density and performance are improved, but parasitic capacitance between source/drain regions and gate structures increases
Solution Approach 1:
The patent introduces a spacer structure as an intermediary element positioned between the source/drain region and the gate structure. This spacer acts as a mediator that reduces direct capacitive coupling while allowing the device to maintain its scaled-down dimensions for high density and performance.
Solution Approach 2:
The patent extracts or removes the harmful capacitive coupling effect by introducing a physical separation structure (spacer) that takes out the direct interaction between source/drain and gate, thereby reducing parasitic capacitance while preserving the benefits of device scaling.
2Quantity of substance
If device dimensions are reduced to increase density, then storage capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the device structure by introducing a distinct spacer component between existing structures. This segmentation allows for modular fabrication processes where the spacer can be formed as a separate element, potentially simplifying the overall manufacturing of scaled-down high-density devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces parasitic capacitance, thereby enhancing the performance of FET devices by minimizing capacitive coupling and improving operational efficiency at high frequencies.
Implementation Method 1
reduce capacitive coupling and parasitic capacitance by 20% to 60%
Implementation Method 2
inner spacer structures made of low-k dielectric materials or air-gaps
Data Source
AI summary
The structure of a semiconductor device with inner spacer structures between source/drain (S/D) regions and gate-all-around structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate and first and second source/drain (S/D) regions disposed on the substrate. Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions. The semiconductor device further includes a gate-all-around (GAA) structure disposed between the first and second S/D regions and wrapped around each of the second nanostructured regions, a first inner spacer disposed between an epitaxial sub-region of the first S/D region and a gate sub-region of the GAA structure, a second inner spacer disposed between an epitaxial sub-region of the second S/D region and the gate sub-region of the GAA structure, and a passivation layer disposed on sidewalls of the first and second nanostructured regions.