Gate-All-Around Varactor Layout With Backside Nanoribbon Taps
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Solution Overview
Problem
The challenge in integrated circuit manufacturing lies in scaling multi-gate and nanowire transistors below the 10 nanometer node, where there is a trade-off between feature dimension and spacing, and existing designs lack a solution for nanowire/nanoribbon architectures to incorporate varactors with efficient backside connections.
Innovation Solution
The development of gate-all-around integrated circuit structures with varactors that employ highly doped nanoribbons and silicon islands, enabling backside metal connections and continuous capacitance tuning, allowing for improved charge transfer and reduced resistance through the use of SiGe and high-k dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate and nanowire transistors are scaled below the 10 nanometer node, then device density and capacity are improved, but the trade-off between critical dimension and spacing constraints becomes overwhelming
Solution Approach 1:
The patent implements gate-all-around structures where the gate electrode completely surrounds the channel region in three dimensions, transitioning from planar 2D gating to 3D wrapping geometry. This dimensional change enables better electrostatic control at scaled dimensions while maintaining feasible lithographic spacing, as the gate controls the channel from all directions rather than just one surface.
Solution Approach 2:
The patent employs nested structures where the gate electrode is positioned within a gate trench that is itself surrounded by isolation structures, and the channel region is nested within the gate-all-around configuration. This nesting approach allows multiple functional elements to be compactly arranged, improving device density while maintaining necessary spacing between adjacent devices through the surrounding isolation structures.
2Ease of manufacture
If conventional tri-gate fabrication processes are used on bulk silicon substrates, then manufacturing cost is reduced and process complexity is simplified, but mobility improvement and short channel control deteriorate at sub-10nm dimensions
Solution Approach 1:
The patent employs composite material structures including high-k dielectric materials combined with metal gate electrodes, and silicon-germanium (SiGe) sacrificial layers combined with silicon channel regions. The high-k dielectric provides superior gate control with thinner effective oxide equivalent, while SiGe layers enable selective removal to release suspended nanowire channels, achieving both ease of manufacture through standard epitaxial processes and reliable short-channel control through enhanced electrostatics.
Solution Approach 2:
The patent uses SiGe sacrificial layers as intermediary structures during fabrication. These SiGe layers are deposited between the silicon channel and substrate, then selectively removed to release and suspend the channel, enabling the gate to wrap around all surfaces. This intermediary approach simplifies the overall process compared to direct nanowire manipulation while achieving the desired 3D gate configuration for improved short-channel control.
3Productivity
If nanowire dimensions are reduced to increase device density, then capacity is improved, but the constraints on lithographic patterning processes become overwhelming
Solution Approach 1:
The patent performs preliminary patterning of the gate trench and isolation structures before forming the actual nanowire channels. The gate-all-around structure is established in advance using standard lithographic patterning at relaxed dimensions, and the nanowire channels are subsequently formed and suspended within this pre-configured framework. This preliminary action allows the use of conventional lithography for the majority of the structure, avoiding the need to directly pattern features at the ultimate nanowire scale.
Solution Approach 2:
The patent introduces sacrificial SiGe layers as intermediary structures that simplify the patterning process. These layers are deposited and patterned at relatively relaxed dimensions using standard lithography, then selectively removed to release the nanowire channels. This intermediary approach decouples the lithographic patterning requirements from the final nanowire dimensions, allowing conventional lithography to produce structures that enable much smaller effective channel dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the quality factor 'Q' of varactors, improving power efficiency and enabling robust functionality of scaled nanowire or nanoribbon transistors with low power consumption and high performance.
Implementation Method 1
enhances the quality factor 'Q' of varactors, improving power efficiency and enabling robust functionality of scaled nanowire or nanoribbon transistors with low power consumption and high performance
Implementation Method 2
allowing for improved charge transfer and reduced resistance through the use of SiGe and high-k dielectric layers
Data Source
AI summary
Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.