Multi-Region Channel Structure for Scaled Semiconductor Transistors
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Solution Overview
Problem
The integration of semiconductor devices leads to challenges in manufacturing transistors with superior performance due to scaling down, which affects the operating characteristics, and existing technologies struggle to optimize transistors for different regions within a semiconductor device.
Innovation Solution
A semiconductor device is designed with a substrate having multiple regions, each with distinct channel structures and gate electrodes, including vertically stacked channel patterns made of different semiconductor materials, and dielectric layers that conformally cover uneven sidewalls, allowing for optimized transistor properties across regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to achieve higher integration, then device density increases, but operating characteristics deteriorate
Solution Approach 1:
The patent applies local quality by implementing different channel structures in different regions of the semiconductor device. Specifically, a first channel structure with vertically stacked channel patterns is used in a first region, while a second channel structure with a single channel pattern is used in a second region. This allows each region to be optimized for specific operating characteristics while maintaining high overall integration density.
2Reliability
If transistors are optimized for specific regions, then operating characteristics improve, but device complexity increases
Solution Approach 1:
The patent segments the semiconductor device into multiple regions (first region, second region, third region) with different channel structures. The first channel structure includes multiple stacked channel patterns, the second channel structure includes a single channel pattern, and the third channel structure includes alternating stacked patterns. This segmentation allows independent optimization of each region while managing overall device complexity through systematic design.
Data Source
AI summary
A semiconductor device including a substrate that includes first to third regions; a first channel structure on the first region and including first channel patterns that are vertically stacked on the substrate; a second channel structure on the second region and including a second channel pattern on the substrate; a third channel structure on the third region and including third channel patterns and fourth channel patterns that are vertically and alternately stacked on the substrate; first to third gate electrodes on the first to third channel structures; and first to third source/drain patterns on opposite sides of the first to third channel structures, wherein the first, second, and fourth channel patterns include a first semiconductor material, and the third channel patterns include a second semiconductor material different from the first semiconductor material.