Multi-Channel Semiconductor Structure With Protective Contact Layer
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices poses challenges in manufacturing fine patterns and reducing size limitations, particularly in developing three-dimensional structure channel FinFETs to enhance operating characteristics.
Innovation Solution
A semiconductor device design featuring a substrate with vertically spaced channel layers, a gate structure intersecting the active region, inner spacer layers, and a conductive or insulating protective layer to improve electrical characteristics by reducing resistance between the source/drain region and channel layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the contact area between source/drain region and channel layers is increased to reduce resistance, then electrical performance is improved, but device complexity increases due to additional protective layer structures
Solution Approach 1:
A conductive protective layer is introduced as an intermediary element between the source/drain region and the channel layers. This layer serves as a mediator that improves electrical contact and reduces resistance while maintaining a clear structural organization. The conductive material acts as a bridge that facilitates charge carrier transport between the source/drain region and multiple channel layers.
Solution Approach 2:
The protective layer extends in the vertical dimension to contact multiple channel layers simultaneously. By positioning the conductive protective layer to extend vertically and contact the side surfaces of multiple channel layers, the design increases the contact area without proportionally increasing planar footprint, thus improving electrical performance while controlling device complexity.
2Reliability
If vertically spaced channel layers are implemented to improve electrical characteristics, then operating performance is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The channel structure is segmented into multiple vertically spaced channel layers rather than a single continuous channel. This segmentation allows each channel layer to be independently formed and positioned at controlled vertical intervals, improving electrical characteristics through multi-layer conduction paths while enabling staged manufacturing processes that can achieve precise vertical spacing.
Solution Approach 2:
Different vertical regions of the device are assigned different functional qualities. The channel layers are positioned at specific vertical heights to optimize electrical characteristics, with each layer serving a specific conduction function. The protective layer is selectively positioned to contact specific channel layers, creating local optimization of electrical performance without requiring uniform precision throughout the entire structure.
Data Source
AI summary
A semiconductor device includes an active region extending in a first direction on a substrate; a plurality of channel layers on the active region and spaced apart from each other in a vertical direction that is perpendicular to the first direction; a gate structure on the substrate, the gate structure intersecting the active region and the plurality of channel layers, extending in a second direction crossing the first direction, and respectively surrounding the plurality of channel layers; inner spacer layers on both sides of the gate structure in the first direction, and on respective lower surfaces of the plurality of channel layers; a protective layer in contact with the inner spacer layers, the plurality of channel layers, and the active region; and a source/drain region on the active region, on at least one side of the gate structure, and in contact with the inner spacer layers.