Backside Self-Aligned Power Rail for Dense Low-Resistance GAA
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Solution Overview
Problem
Conventional gate-all-around (GAA) devices face performance degradation due to low gate density and high resistance, particularly with existing power rail schemes on the front side of the substrate, which also suffer from short circuit issues between the metal gate and power rail, and between the source and drain regions.
Innovation Solution
A self-aligned backside power rail scheme is introduced, utilizing a bottom dielectric layer to control via position and prevent short circuits, thereby improving the reliability and performance of GAA devices by increasing gate density and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power rails are formed on the front side of the substrate using existing schemes, then power distribution is achieved, but the density is low and resistance is high due to process limitations
Solution Approach 1:
The patent inverts the conventional power rail formation approach by moving power rail formation from the front side to the back side of the semiconductor substrate. This inversion allows power rails to be formed after transistor fabrication, enabling higher density and lower resistance while avoiding interference with front-side device structures.
Solution Approach 2:
The patent transitions power rail formation from the two-dimensional front-side plane to the three-dimensional backside surface, utilizing the vertical dimension and backside area to achieve higher power rail density without compromising front-side device performance.
2Reliability
If power rails are formed on the front side of the substrate, then power distribution is achieved, but short circuit issues occur between the metal gate and power rail, and between source and drain regions
Solution Approach 1:
By inverting the power rail formation location to the backside, the patent naturally eliminates short circuit risks between front-side metal gates and power rails, as well as between source and drain regions, since power rails are formed after transistor structures are complete and isolated by the substrate thickness.
Solution Approach 2:
The substrate itself acts as an intermediary barrier between the front-side transistor structures and back-side power rails, providing natural electrical isolation that prevents short circuits while maintaining power distribution functionality.
3Reliability
If device sizes are scaled down to increase gate density, then transistor performance is improved, but the complexity of processing and manufacturing increases
Solution Approach 1:
The patent segments the power distribution function from the transistor fabrication process by forming power rails separately on the backside after transistor completion, allowing independent optimization of both small transistor dimensions and power rail structures without mutual interference.
Solution Approach 2:
By utilizing the backside dimension for power rail formation, the patent decouples power distribution complexity from front-side transistor scaling, enabling continued miniaturization of transistors without proportionally increasing overall manufacturing complexity.
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.