Nano-FET Gate Stack with Merged Work Function Metals
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Solution Overview
Problem
In advanced semiconductor manufacturing, the deposition of barrier layers in nano-FETs is challenging due to small feature sizes, leading to manufacturing defects and complexity, while omitting these layers allows for improved manufacturing ease without significantly impacting electrical performance.
Innovation Solution
Omitting the barrier layer between work function metal layers in nano-FET gate stacks, allowing them to merge, simplifies the manufacturing process and reduces defects, as thickness variations do not significantly affect the electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If barrier layers are deposited between work function metal layers, then manufacturing precision is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent removes the barrier layer from the gate stack structure between work function metal layers. By extracting this layer, the patent simplifies the manufacturing process and reduces structural complexity while maintaining acceptable electrical performance, directly addressing the contradiction between precision and complexity
Solution Approach 2:
Instead of following the conventional approach of adding barrier layers to prevent metal diffusion, the patent inverts the approach by allowing direct contact between work function metal layers and relying on process control and material selection to prevent unwanted diffusion, thereby simplifying the structure
2Manufacturing precision
If barrier layers are deposited between work function metal layers, then manufacturing precision is improved, but ease of manufacture deteriorates
Solution Approach 1:
The patent extracts the barrier layer from the manufacturing process, eliminating the deposition steps and associated process controls required for barrier layer formation. This directly improves ease of manufacture while the patent compensates for the lost precision protection through alternative process controls
Solution Approach 2:
The patent discards the barrier layer component and recovers the manufacturing simplicity it provides. The electrical performance that would have been protected by the barrier layer is maintained through careful control of the work function metal layer properties and deposition processes
3Area of moving object
If minimum feature sizes are reduced, then integration density is improved, but manufacturing precision deteriorates
Solution Approach 1:
The patent addresses the precision challenge at reduced feature sizes by moving control to the vertical dimension through careful control of thin film deposition thicknesses and profiles, rather than relying solely on lateral dimensional control that becomes increasingly difficult at smaller feature sizes
Data Source
AI summary
A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric disposed around the first nanostructure; a second high-k gate dielectric being disposed around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises a first portion of a p-type work function metal filling an area between the first high-k gate dielectric and the second high-k gate dielectric.