Backside Power Rail Contact Layout With Air Gap for Lower Capacitance
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Solution Overview
Problem
The increasing demand for lower power consumption, higher performance, and smaller area in semiconductor devices leads to challenges in reducing parasitic capacitance and resistance, which degrades the performance of backside power rail (BPR) semiconductor devices due to the introduction of parasitic capacitance between the gate structure and dummy front-side S/D contact structures.
Innovation Solution
The implementation of an air gap between the second S/D region and the gate structures in BPR semiconductor devices, achieved by removing the metal contact and silicide layer of the second S/D contact structure and forming a seal dielectric structure to seal the air gap, reduces parasitic capacitance and improves device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dummy front-side S/D contact structures are introduced in BPR semiconductor devices, then manufacturing process is simplified, but parasitic capacitance between gate structure and contact structures increases degrading device performance
Solution Approach 1:
The patent extracts and removes the harmful dummy front-side S/D contact structures from the device architecture. By eliminating these structures that cause parasitic capacitance, the invention resolves the contradiction between manufacturing simplicity and performance degradation, achieving both ease of manufacture (through alternative simplified processes) and reduced parasitic capacitance.
Solution Approach 2:
The patent converts the harmful effect of parasitic capacitance into a benefit by introducing air gaps that exploit the low dielectric constant of air. The air gaps transform the problematic capacitance issue into an opportunity for capacitance reduction, thereby converting the harmful factor into a beneficial design feature that improves device performance.
2Area of moving object
If device dimensions are scaled down to meet higher storage capacity and processing speed demands, then device area is reduced, but parasitic capacitance and resistance increase degrading performance
Solution Approach 1:
The patent applies local quality by introducing air gaps specifically in critical regions where parasitic capacitance has the most impact, such as between the gate structure and S/D contact structures. This localized modification allows the device to maintain small overall dimensions while reducing parasitic effects in specific areas, resolving the contradiction between area reduction and performance degradation.
Solution Approach 2:
The patent changes the dielectric parameter by introducing air gaps with low dielectric constant into the device structure. This parameter change reduces parasitic capacitance without increasing device area, as the air gaps utilize existing spaces rather than adding bulk material. The modified capacitance parameter directly addresses the performance degradation issue while maintaining compact dimensions.
3Reliability
If air gap is introduced to reduce parasitic capacitance, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming air gaps during earlier manufacturing stages when the structure is more accessible and easier to modify. By creating air gaps before subsequent processing steps, the invention simplifies the overall manufacturing process despite the added feature, as later steps can proceed without additional complexity. This timing strategy resolves the contradiction between performance improvement and manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a performance improvement of BPR semiconductor devices by about 3% to 5.5% due to capacitance reduction, effectively addressing the parasitic capacitance issue and enhancing device performance.
Implementation Method 1
parasitic capacitance between the gate structure and dummy front-side S/D contact structures
Implementation Method 2
an air gap between the gate structure and the second S/D contact structure reduces parasitic capacitance
Data Source
AI summary
The present disclosure describes a method to form a backside power rail (BPR) semiconductor device with an air gap. The method includes forming a fin structure on a first side of a substrate, forming a source/drain (S/D) region adjacent to the fin structure, forming a first S/D contact structure on the first side of the substrate and in contact with the S/D region, and forming a capping structure on the first S/D contact structure. The method further includes removing a portion of the first S/D contact structure through the capping structure to form an air gap and forming a second S/D contact structure on a second side of the substrate and in contact with the S/D region. The second side is opposite to the first side.