CFET Power Switch Circuit for Fast Wake-Up in Compact ICs
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Solution Overview
Problem
Existing power switches with strong wake-up force occupy a large area in circuit systems, hindering the advancement of integrated circuit (IC) devices, as they require a balance between wake-up speed and area efficiency, especially during mode transitions from sleep to normal operation.
Innovation Solution
A novel power switch architecture utilizing complementary field-effect transistors (CFETs) with interleaving n-type and p-type nanowires, where the power switch circuit provides an intermediate supply voltage, optimizing wake-up time without increasing the semiconductor wafer area, by reconfiguring dummy areas into functional transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a power switch with strong wake-up force is used, then the operating speed is improved, but the area occupied increases
Solution Approach 1:
The patent implements CFET structures where n-type and p-type transistors are stacked vertically in three dimensions, allowing the power switch to achieve strong wake-up force without increasing lateral area occupancy. The vertical stacking enables higher drive current density while maintaining compact footprint
Solution Approach 2:
The patent merges n-type and p-type transistor functions into a single integrated CFET structure, where both transistor types share common source/drain regions and control electrodes. This consolidation achieves the required wake-up force while reducing the total area compared to separate transistor implementations
2Area of stationary object
If dummy areas are reconfigured into functional transistors, then the area efficiency is improved, but the device complexity increases
Solution Approach 1:
The patent designs CFET structures where control electrodes serve multiple functions: controlling both n-type and p-type transistor channels, providing intermediate supply voltage, and enabling wake-up functionality. This multi-functionality converts what would be dummy areas into highly efficient functional elements without proportionally increasing complexity
Solution Approach 2:
The patent segments the CFET structure into distinct functional regions including n-type channel portions, p-type channel portions, and shared control electrode portions. This segmentation allows independent optimization of each region while maintaining overall area efficiency and managing fabrication complexity
Data Source
AI summary
An integrated circuit device includes: an integrated circuit module; a first field-effect transistor coupled between the integrated circuit module and a first reference voltage, and controlled by a first controlled signal; and a second field-effect transistor coupled between the integrated circuit module and the first reference voltage; wherein the second field-effect transistor is a complementary field-effect transistor of the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor are configured to generate a second reference voltage for the integrated circuit module according to the first control signal.