Stacked FET Bottom EPI Contact Wraparound Structure
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Solution Overview
Problem
In stacked semiconductor devices, achieving a sufficient contact surface area between the lower transistor and an electrical contact without increasing the device footprint is challenging, as traditional scaling methods are limited in enhancing device density.
Innovation Solution
The solution involves undercutting the lower device to allow the electrical contact to wrap around it, ensuring direct contact with multiple sides of the lower source/drain epi, thereby increasing the contact surface area without expanding the device footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional scaling methods are used to increase device density, then device density improves, but contact surface area between lower transistor and electrical contact decreases
Solution Approach 1:
The patent transitions from a planar contact interface to a three-dimensional contact structure by allowing the electrical contact to wrap around and contact multiple side surfaces of the lower source/drain epi. This dimensional change enables increased contact surface area without expanding the device footprint, effectively resolving the contradiction between maintaining high device density and ensuring sufficient contact surface area.
2Area of stationary object
If device footprint is increased to improve contact surface area, then contact surface area improves, but device density decreases
Solution Approach 1:
The patent utilizes vertical and lateral wrapping of the electrical contact around the lower source/drain epi structure to access multiple side surfaces. This approach increases contact surface area within the existing device footprint by exploiting three-dimensional space, thereby maintaining high device density while achieving sufficient contact area without requiring additional horizontal space.
Solution Approach 2:
The electrical contact is configured to wrap around and nest within the spatial envelope of the lower source/drain epi structure, contacting multiple side surfaces in a nested arrangement. This nesting approach maximizes contact surface area within the constrained device footprint, preventing the need to expand the overall device dimensions.
3Ease of manufacture
If electrical contact contacts only top surface of lower source/drain epi, then manufacturing simplicity is maintained, but contact surface area is insufficient
Solution Approach 1:
The patent divides the contact interface into multiple discrete contact regions on different side surfaces of the lower source/drain epi. By segmenting the contact structure to engage with multiple faces (front, rear, and side surfaces) rather than a single top surface, the total contact surface area is increased while maintaining relatively straightforward manufacturing through sequential processing steps.
Data Source
AI summary
A stacked semiconductor device comprising a lower source/drain epi located on top of a bottom dielectric layer. An isolation layer located on top of the lower source/drain epi and an upper source/drain epi located on top of the isolation layer. A lower electrical contact that is connected to the lower source/drain epi, wherein the lower electrical contact is in direct contact with multiple side surfaces of the lower source/drain epi.