Nanosheet Source/Drain Epitaxy With Graded SiGe for Strain Control
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in integrating more components into a given area while maintaining device performance and reliability, particularly in forming efficient source/drain regions and gate structures.
Innovation Solution
A multi-layer structure is formed using alternating layers of semiconductor materials with different lattice constants, followed by a series of etching and deposition processes to create nanostructure fins and source/drain regions, including the use of spacer materials and recess etching to define channel interfaces and source/drain structures, allowing for precise control of germanium concentration and strain effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but device performance and reliability deteriorate
Solution Approach 1:
The patent applies local quality by creating alternating layers of semiconductor materials with different properties (e.g., Si/SiGe) where specific regions have different lattice constants and strain characteristics. This allows different parts of the device to have optimized local properties for carrier mobility and stress control, maintaining performance despite reduced feature sizes.
Solution Approach 2:
The patent changes material parameters by using alternating layers with different lattice constants and germanium concentrations. This enables control of strain and stress fields within the channel region, optimizing carrier mobility and device performance at scaled dimensions through parameter optimization rather than simply reducing size.
2Quantity of substance
If feature size is reduced to increase integration density, then more components fit in given area, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent segments the semiconductor structure into alternating thin layers of different materials (Si/SiGe/Si) with controlled thicknesses. This segmentation approach allows precise control of each layer's thickness and composition, enabling accurate feature size control through layer-by-layer fabrication processes.
Solution Approach 2:
The patent transitions from controlling only lateral dimensions to incorporating vertical dimension control through alternating layers. By precisely controlling layer thicknesses in the vertical dimension, the patent achieves overall feature size precision that compensates for challenges in lateral dimension control at scaled sizes.
3Reliability
If complex etching and deposition processes are used to create nanostructure fins and source/drain regions, then device performance is improved through strain control, but device complexity increases
Solution Approach 1:
The patent performs preliminary action by forming the alternating Si/SiGe/Si layer structure before creating the fin and source/drain regions. This pre-formed layered structure provides built-in strain and stress fields that will be activated during subsequent processing, eliminating the need for complex post-formation strain engineering steps.
Solution Approach 2:
The alternating SiGe layers act as intermediaries that mediate between the substrate and the channel region. These intermediate layers provide the necessary strain and stress fields to enhance carrier mobility without requiring direct manipulation of the channel structure, simplifying the overall process complexity.
Data Source
AI summary
Semiconductor devices and methods of fabrication are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin and into a substrate as an initial step in forming a source/drain region. A first semiconductor material is epitaxially grown from channels exposed along sidewalls of the opening to form first source/drain structures. A second semiconductor material is epitaxially grown from the first semiconductor material to form a second source/drain structure over and to fill a space between the first source/drain structures. A bottom of the second source/drain structure is located below a bottommost surface of the first source/drain structures. The second semiconductor material has a greater concentration percentage by volume of germanium than the first semiconductor material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the nanostructures.