Gate Isolation Structure for Endcap-Free Nanosheet FETs
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Solution Overview
Problem
As semiconductor device dimensions are scaled down, it becomes difficult to form contacts and vias to the gate, source, and drain electrodes of field-effect transistors due to increased active area spacing and the presence of endcaps, which hinder performance and increase complexity in manufacturing.
Innovation Solution
A self-aligned gate isolation structure is formed by recessing a first gate metal, selectively growing a second gate metal, and depositing the gate isolation structure between the gate and neighboring gate structures, with an anneal process using oxygen to increase the lateral thickness of the interfacial layer, allowing for reduced thickness of the second gate metal and improved device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate structures are used with endcaps, then manufacturing is simpler, but device performance deteriorates and chip area increases
Solution Approach 1:
The patent removes the endcap structure from the gate electrode, extracting the harmful element that caused performance degradation. The gate electrode is terminated at the channel edges without extending beyond, eliminating the endcap-induced performance issues while maintaining structural integrity through proper alignment and isolation structures.
Solution Approach 2:
The patent performs preliminary alignment and positioning of the gate electrode relative to the channel structure before final formation. By establishing precise alignment early in the fabrication process and using self-aligned techniques, the complex positioning requirements are addressed beforehand, simplifying subsequent manufacturing steps.
2Productivity
If device dimensions are scaled down, then production efficiency increases and costs decrease, but manufacturing difficulty increases due to active area spacing and endcap formation
Solution Approach 1:
The patent applies different structural characteristics to different regions of the device. The gate electrode has zero endcap length at the channel edges, while the interfacial layer has increased lateral thickness in specific regions. This localized differentiation allows scaling benefits while managing manufacturing challenges through region-specific optimization.
Solution Approach 2:
The patent modifies the interfacial layer thickness parameter, increasing its lateral thickness to compensate for the reduced gate endcap. This parameter change in the interfacial layer maintains proper electrical isolation and device performance during scaling, addressing manufacturing difficulties without sacrificing productivity gains.
3Reliability
If endcap area is reduced, then device performance improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs self-aligned fabrication techniques where the gate electrode automatically positions itself relative to the channel structure without requiring high-precision external alignment. The interfacial layer and isolation structures serve as self-aligning references, eliminating the need for complex alignment procedures and reducing manufacturing precision requirements while maintaining zero endcap geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the endcap area, enhances the performance of nanostructure devices, and increases the integration density of semiconductor devices by minimizing the chip area, thereby improving manufacturing efficiency and device performance.
Implementation Method 1
an anneal process using oxygen to increase the lateral thickness of the interfacial layer
Implementation Method 2
an anneal process using oxygen to increase the lateral thickness of the interfacial layer
Data Source
AI summary
A device includes a first vertical stack of first nanostructures formed over a substrate, a second vertical stack of second nanostructures adjacent to the first vertical stack, and a first gate structure adjacent the first nanostructures. The first gate structure includes a first gate portion between the first nanostructures, and a second gate portion extending from a first sidewall of the first gate portion to a second sidewall of the first gate portion. The second sidewall is between the first sidewall and the substrate, and is a different material than the first gate portion. A second gate structure is adjacent the second nanostructures, and a second wall structure is between the second gate portion and the second gate structure.