Sculpted Fin Nanowire Channels for Gate-All-Around FET Control
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Solution Overview
Problem
As semiconductor technology advances to sub-10 nm nodes, gate-all-around (GAA) FETs face challenges in achieving full control over the channel region due to the lack of gate control over the bottom side of the fin structure, leading to short-channel effects and performance limitations.
Innovation Solution
The method involves forming nanowire structures for channel regions without a stack of semiconductor layers, where the fin structure is sculpted to have non-etched and etched portions, oxidized to form nanowires, and then releasing them, allowing for a gate dielectric layer and gate electrode to surround each nanowire, thereby enhancing control over the channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate electrode is placed adjacent to three side surfaces of a channel region (Fin FET configuration), then the transistor achieves three-gate control, but the fourth side (bottom part of channel) remains far from the gate electrode resulting in poor gate control and short-channel effects
Solution Approach 1:
The patent transitions from a planar three-side gate configuration to a three-dimensional gate-all-around configuration where the gate electrode completely surrounds the channel region including the bottom side. This dimensional change enables the gate to control all surfaces of the channel, eliminating the short-channel effects that plague conventional Fin FETs where the bottom side is inaccessible to gate control.
2Productivity
If transistor dimensions are scaled down to sub 10 nm technology nodes, then device density and performance are improved, but short-channel effects and performance limitations worsen due to inadequate gate control
Solution Approach 1:
By implementing gate-all-around architecture, the patent provides omnidirectional gate control that becomes increasingly effective as channel dimensions shrink to sub-10 nm nodes. The three-dimensional configuration ensures that even at ultra-scaled dimensions, the gate maintains authoritative control over the entire channel perimeter, suppressing short-channel effects that would otherwise dominate at these aggressive technology nodes.
Solution Approach 2:
The gate electrode is positioned to completely enclose the channel region, with the gate dielectric layer interposed between the gate and channel. This nested configuration creates a hierarchical structure where the gate surrounds the channel in all directions, providing maximum electrostatic control and enabling the device to achieve full depletion and reduced short-channel effects even at sub-10 nm scales.
3Reliability
If a gate-all-around FET structure is implemented to surround all side surfaces of the channel region, then fuller depletion and reduced short-channel effects are achieved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the gate structure into distinct components: a gate dielectric layer and a gate electrode layer, with the gate electrode patterned to surround the channel region on all sides. This segmentation allows for systematic fabrication using sequential deposition and patterning steps, making the complex three-dimensional gate-all-around structure manufacturable through established semiconductor processing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves gate control over the channel region, reducing short-channel effects and enhancing performance by allowing for fuller depletion and better sub-threshold current swing and drain-induced barrier lowering.
Implementation Method 1
The sculpted fin structure is oxidized so that a plurality of nanowires are formed in the plurality of non-etched portions, respectively, and the plurality of etched portions are oxidized to form a plurality of oxides
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure is sculpted to have a plurality of non-etched portions and a plurality of etched portions having a narrower width than the plurality of non-etched portions. The sculpted fin structure is oxidized so that a plurality of nanowires are formed in the plurality of non-etched portions, respectively, and the plurality of etched portions are oxidized to form oxides. The plurality of nanowires are released by removing the oxides.