2D Semiconductor Contacts Using Fermi-Level Pinning and Depinning

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Solution Overview

Problem

Current semiconductor devices face challenges in miniaturization due to performance degradation, and there is a need for improved integration and simplified fabrication processes, particularly in forming contacts with two-dimensional (2D) materials.

Innovation Solution

A semiconductor device is designed with a first and second 2D material layer, where Fermi-level pinning and depinning are achieved on interfacial surfaces using a single metal electrode, allowing for different contact types and simplifying the fabrication process by using an intermediate layer such as amorphous carbon, graphene, or hexagonal boron nitride, enabling efficient contact formation without complex wiring structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If different contact types (n-type and p-type) are formed using different metal electrodes, then contact performance is optimized, but device complexity and fabrication process complexity increase

Engineering Contradiction:
Improvecontact performanceVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A single metal electrode material is designed to perform multiple functions by forming different contact types (n-type and p-type) with different 2D material layers. The first metal electrode forms an n-type contact with the first 2D material layer and a p-type contact with the second 2D material layer, eliminating the need for separate metal electrodes for different contact types and simplifying the fabrication process.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

Different contact types are achieved by exploiting the different electronic properties of different 2D material layers at the same metal electrode interface. The first 2D material layer interface is engineered to provide n-type contact characteristics, while the second 2D material layer interface provides p-type contact characteristics, allowing local differentiation of contact properties without changing the metal electrode material.

Inventive Principle:
Principle #3Local quality

2Reliability

If Fermi-level pinning is used to form contacts, then contact stability is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvecontact stabilityVSAvoidinterface quality control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The Fermi level position is controlled by changing the material composition and electronic structure of different 2D material layers. By selecting specific 2D materials with appropriate band structures and doping characteristics, the Fermi level is pinned at desired positions to achieve stable n-type or p-type contacts without requiring extreme manufacturing precision.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables the formation of different contact types with a single metal electrode, enhancing the performance and integration of 2D material-based semiconductor devices while reducing the short channel effect and simplifying the manufacturing process, even at small thicknesses of about 1 nm or less.

Implementation Method 1

A Fermi-level may be pinned on an interfacial surface between the first 2D material layer and the first electrode

Methodology Applied
Scientific EffectFermi-level pinning:

Implementation Method 2

The Fermi-level may be depinned on an interfacial surface between the second 2D material layer and the first electrode

Methodology Applied
Scientific EffectFermi-level depinning:

Data Source

PatentUS20240170562A1Semiconductor device including two-dimensional material and method of fabricating the same
Publication Date: 2024.05.23 SAMSUNG ELECTRONICS CO LTD
  • US20240170562A1 patent drawing
  • US20240170562A1 patent drawing
  • US20240170562A1 patent drawing

AI summary

A semiconductor device may include a first two-dimensional (2D) material layer, a second 2D material layer, a first electrode, a second electrode, a third electrode, a first gate electrode. and a second gate electrode. A Fermi-level may be pinned on an interfacial surface between the first 2D material layer and the first electrode. The Fermi-level may be depinned on an interfacial surface between the second 2D material layer and the first electrode.