2D Material FET Contacts Without Fermi Level Pinning

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Solution Overview

Problem

The performance of two-dimensional (2D) semiconductor transistors is limited by the strong Fermi level pinning effect at interfaces between metal contacts and 2D materials due to metal-induced gap states (MIGS), which affects the efficiency of field effect transistors (FETs).

Innovation Solution

A method for manufacturing a FET that involves forming a gate electrode, gate dielectric layer, and channel layer on a substrate, followed by the sequential formation of an insulating layer, etching stop layer, and protective layer, with a plasma treatment step to remove dangling bonds on the channel layer, thereby avoiding Fermi level pinning at the metal-semiconductor interface. This method uses 2D materials like graphene or transition metal dichalcogenides (TMDs) as the channel layer and forms source and drain electrodes using plasma atomic layer deposition (ALD) to enhance contact bonding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If plasma treatment is applied to remove dangling bonds, then Fermi level pinning is avoided, but additional processing steps are required

Engineering Contradiction:

ImproveFermi level pinning-free interfaceVSAvoidprocessing steps

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The insulating layer is formed in advance before metal contact deposition, preliminarily preventing the formation of harmful interface states. This preliminary action of introducing the insulating layer eliminates the need for subsequent plasma treatment or other complex surface modification steps to remove dangling bonds, as the insulating layer already prevents their formation at the metal-2D materials interface.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The approach results in improved carrier mobility and reduced short-channel effects, achieving a Fermi level pinning-free interface with enhanced electrostatic control and increased reliability of the FET, leading to better performance and stability of the integrated circuit.

Implementation Method 1

a plasma treatment step to remove dangling bonds on the channel layer

Methodology Applied

Scientific EffectPlasma etching: Plasma

Implementation Method 2

forms source and drain electrodes using plasma atomic layer deposition (ALD)

Methodology Applied

Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Data Source

PatentUS12113119B2Field effect transistor, preparation method thereof and integrated circuit

Publication Date: 2024.10.08 HON HAI PRECISION INDUSTRY CO LTD

AI summary

An FET, a method for manufacturing such FET, and an integrated circuit are disclosed. The FET includes a substrate carrying a gate electrode, a gate dielectric layer, and a channel layer sequentially stacked on the substrate. An insulating layer, an etching stop layer, and a protective layer are stacked sequentially on the channel layer. Source and drain electrodes are also formed. A material of the channel layer includes a 2D material. The FET defines two through holes extending through the insulating layer, the etching stop layer, and the protection layer and the channel layer is exposed, the two through holes carry the source and drain electrodes to form a top or direct contact with the channel layer.