2D Interconnect Capping Layers for Electromigration Reliability
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) are scaled down, the increased capacitance due to reduced spacing between conductive features leads to higher power consumption and time delay, and the reliability of interconnect structures is compromised by increased resistivity and electromigration, particularly as the width of interconnect conductive structures decreases.
Innovation Solution
The use of a first capping layer comprising a two-dimensional material such as graphene or hexagonal boron nitride over the interconnect conductive structure to reduce resistivity and electromigration, accompanied by a second capping layer with better adhesion properties to mitigate structural integrity issues and facilitate the deposition of other layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the width of interconnect conductive structures is decreased to increase density, then the capacitance increases leading to higher power consumption and time delay, but the spacing between elements is reduced to increase density
Solution Approach 1:
The patent applies different materials with specific local properties to different regions of the interconnect structure. Low-k dielectric material is used in specific regions to reduce capacitance, while copper or cobalt conductive materials are used in interconnect structures to reduce resistivity. This local optimization allows density increase without proportionally increasing power consumption.
Solution Approach 2:
The patent employs composite material structures combining multiple materials with complementary properties. The interconnect structure uses copper or cobalt conductors combined with low-k dielectric materials, and further combines these with capping layers of tungsten, tungsten nitride, or tungsten silicide. This composite approach optimizes both capacitance reduction and power consumption.
2Quantity of substance
If the width of interconnect conductive structures is decreased to increase density, then the capacitance increases leading to higher time delay, but the spacing between elements is reduced to increase density
Solution Approach 1:
The patent applies low-k dielectric material specifically in the interconnect structure regions where capacitance affects signal delay. This localized application reduces the capacitance between adjacent conductive structures, thereby reducing time delay while maintaining high element density.
Solution Approach 2:
The patent changes the dielectric constant parameter by using low-k dielectric materials with lower permittivity values. This parameter change directly reduces capacitance (C = εA/d), thereby reducing time delay (τ = RC) while maintaining the reduced spacing required for high density.
3Quantity of substance
If the width of interconnect conductive structures is decreased, then the resistivity increases compromising reliability, but the spacing is reduced to increase density
Solution Approach 1:
The patent applies copper or cobalt materials specifically in the interconnect conductive structures where current flow occurs. These materials have lower resistivity compared to traditional aluminum, which compensates for the increased resistivity effect of reduced width and maintains reliability.
Solution Approach 2:
The patent creates a composite interconnect structure combining copper or cobalt conductors with low-k dielectric materials and capping layers. This composite structure optimizes electrical properties by selecting materials with appropriate conductivity and protective properties, maintaining reliability despite reduced dimensions.
4Reliability
If a first capping layer is added to reduce resistivity and electromigration, then the reliability is improved, but the structural integrity may be compromised without a second capping layer with better adhesion
Solution Approach 1:
The patent divides the capping layer function into two separate layers: a first capping layer (tungsten, tungsten nitride, or tungsten silicide) that provides electromigration protection and resistivity reduction, and a second capping layer that provides adhesion and structural integrity. This segmentation allows each layer to optimize its specific function without compromising the other.
Solution Approach 2:
The patent creates a composite capping structure using different materials with complementary properties. The first capping layer materials (tungsten-based) provide electrical benefits, while the second capping layer materials provide mechanical adhesion and structural stability. This composite approach resolves the contradiction between reliability improvement and structural integrity maintenance.
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. A first interconnect conductive structure extends through the first interconnect dielectric layer. A first capping layer is arranged over the first interconnect conductive structure, and a second capping layer is arranged over the first capping layer. The first capping layer includes a first two-dimensional material that is different than a second two-dimensional material of the second capping layer. An etch stop layer is arranged over the first interconnect dielectric layer and the second capping layer. The integrated chip further includes a second interconnect dielectric layer arranged over the etch stop layer and a second interconnect conductive structure extending through the second interconnect dielectric layer and the etch stop layer to contact the first interconnect conductive structure.