2D Material Layer for Transistor Channel and RRAM Electrode Integration
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Solution Overview
Problem
Current resistive random access memory (RRAM) and transistor structures face challenges in integrating a 2D material layer effectively as both a channel region and connection element, limiting their performance in terms of conduction speed and energy efficiency.
Innovation Solution
A semiconductor structure is developed where a 2D material layer is used simultaneously in both the transistor and RRAM regions, with the RRAM comprising a lower electrode layer, resistive switching layer, and upper electrode layer sequentially on the 2D material layer, and the 2D material layer acting as the channel region of the transistor, allowing for electrical connection and shared material layer formation to reduce process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a 2D material layer is used as both channel region and connection element in RRAM and transistor structures, then conduction speed and energy efficiency are improved, but device complexity and integration difficulty increase
Solution Approach 1:
The 2D material layer is designed to serve multiple functions simultaneously: it acts as the channel region for the transistor and as the connection element (electrode) for the RRAM structure. This multi-functional design eliminates the need for separate materials for these components, thereby improving conduction speed and energy efficiency while managing integration complexity through functional consolidation.
Solution Approach 2:
The patent merges the 2D material layer into both the transistor channel and RRAM electrode structures, combining what would traditionally be separate components into a unified material system. This merging reduces the number of interfaces and material transitions, improving electron transport and reducing energy consumption while maintaining manufacturability through a shared fabrication process.
2Ease of manufacture
If separate material layers are used for RRAM and transistor components, then manufacturing process is simpler, but energy consumption increases and conduction speed decreases
Solution Approach 1:
The same 2D material layer is utilized for both RRAM electrode and transistor channel functions, creating a universal material solution that reduces energy consumption and improves conduction speed. This approach maintains ease of manufacture by using a single material deposition process rather than requiring multiple specialized material layers.
Solution Approach 2:
The patent changes the material parameter from conventional bulk materials to 2D materials, which fundamentally alters the electrical properties to achieve lower energy consumption and higher conduction speed. This parameter change enables the material to efficiently perform both RRAM and transistor functions while maintaining process simplicity through standard semiconductor fabrication techniques.
3Productivity
If 2D material layer is formed before RRAM and transistor structures, then process steps are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The 2D material layer is formed in advance before the RRAM and transistor structures are built upon it. This preliminary action establishes a common foundation that simplifies subsequent processing steps and reduces overall process complexity, while the self-aligned nature of the 2D material helps manage precision requirements.
Solution Approach 2:
The 2D material layer is selectively positioned and configured in different regions to serve specific functions: as the channel region in the transistor area and as the connection element in the RRAM area. This local differentiation of function within a unified material layer allows for reduced process steps while managing precision requirements through region-specific optimization.
Data Source
AI summary
The present invention provides a semiconductor structure, the semiconductor structure includes a substrate defining a memory region and a transistor region, an insulating layer is disposed on the substrate, a 2D material layer disposed on the insulating layer, and disposed within the memory and the transistor region, parts of the 2D material layer within the transistor region is used as the channel region of a transistor structure, the transistor structure is disposed on the channel region. And a resistive random access memory (RRAM) located in the memory region, the RRAM includes a lower electrode layer, a resistance transition layer and an upper electrode layer being sequentially located on the 2D material layer and electrically connected to the channel region.