Transistor TRIZ Cases

In-situ doped selective growth forms MOSFET source and drain regions with tighter channel-length control and lower junction leakage.

A shared PN-Schottky forward conduction unit cuts reverse recovery charge in parallel LIGBTs, improving switching speed and power efficiency.

A vertical transfer gate and stacked channel structure shrink pixel size while improving electron pull-out efficiency and image quality.

An embedded second amorphous silicon layer in the gate insulator cuts high-voltage leakage current without extra electrodes or lower efficiency.

A stepped conductive-layer layout shortens source-drain spacing beyond exposure limits to raise on-state current and keep fabrication practical.

Shared active regions and conductive links cut parasitic resistance, enabling accurate fuse blowing and status testing in compact semiconductor arrays.

A carbon hardmask enables distinct gate workfunctions for I/O and logic transistors on one substrate without extra mask steps.

Measures gate current during turn-on and turn-off to detect gate oxide failures while maintaining stable high-speed switching.

Reworked package and PCB contacts separate load and sense paths to cut gate-loop magnetic coupling and reduce switching losses.

Active patterns over a sacrificial layer create vertical transistors with buried bit lines, raising memory density without short-channel loss.

Nitrogen doping and in-situ graphene growth turn a metallic TFT channel into a switchable semiconductor with high on/off ratio and low threshold voltage.

Multiple counters inside each pixel capture histograms and extend dynamic range while reducing noise in high-contrast imaging.

Vertically spaced charge-storage and blocking segments limit charge migration between NAND cells, improving data retention and reliability.

Contact-last stacked transistor processing protects lower device layers and improves metal connection quality to cut routing resistance.

Depositing low-k spacer material in etched dimples helps nanowire transistors cut overlap capacitance, leakage, and short-channel effects.

A stacked active-layer memory layout uses gate-all-around word lines and vertical bit lines to raise integration while improving current control.

A segmented SCR layout uses connected regions and tuned overlap to improve trigger uniformity, prevent filamentation, and protect compact chips from ESD.

Lower-level routing in an inverted IC layout frees upper metal resources, shrinking standard cell pitch and area while supporting reliable connectivity.

A gate extension spanning active-region and trench-isolation interfaces cuts SOI edge leakage while limiting capacitance and power loss.

Protruding control gate pad regions increase gate spacing, prevent hard mask merge, and keep word line etching uniform in dense memory arrays.

Separate current sensing and threshold comparison stop overloads at multi-output power terminals before wiring burnout.

Rounded, tapered support protrusions protect flexible display substrates from scratches and friction while preserving bendability and rollability.

Localized particle irradiation raises energy level density under the mesa to cut reverse recovery charge while protecting gate insulating films.

Vertical stacking with shared access and data lines shrinks 2T memory cells to raise density while reducing power dissipation and cost per bit.

Balanced PMOS-NMOS 8T bitcells remove transition regions to shrink multi-ported memory arrays while preserving read stability and scalability.

Gate-cut segmentation separates stacked transistors to shrink 6T SRAM cells while managing precision and structural complexity.

Sealed air gaps between adjacent DRAM bit lines reduce parasitic capacitance, preserving speed as memory cell density increases.

Integrated nanosheets and fins with tuned (100)/(110) crystal planes narrow pFET-nFET mobility gaps and improve pFET transport.

A sacrificial separation layer is replaced with a conductor to link transistor channel stacks, improving signal routing and voltage delivery in 3D ICs.

Vertically stacked semiconductor structures and integrated cooling raise DRAM density while improving carrier mobility and lowering leakage.

Sealed air gaps between adjacent DRAM bit lines reduce parasitic capacitance and coupling, helping dense memory cells maintain speed.

Vertical fin-like channel layers beside stacked gates increase effective transistor width and current gain without much added device area.

Varying subfin etch depths boosts diode cross-section, ESD protection, and current handling in nanoribbon ICs without added process complexity.

Backside power delivery through vertical gate-all-around power gates cuts power resistance and frees front-side routing in scaled ICs.

Opposite-polarity dipole layers let gate-all-around common metal gates tighten N-P boundaries, tune threshold voltage, and simplify metal gate flow.

Selective recess and sacrificial oxidation depopulate lower nanowire channels to tune drive current and curb leakage in scaled gate-all-around ICs.

A ring-shaped peripheral well integrates HVMOS and HVJT on one IC, cutting chip area and avoiding wire-bond reliability issues.

A floating-body memory stores data quickly in volatile mode, then transfers it to a floating gate or trapping layer when power is interrupted.

Selective diffusion gaps and p-type edge implants suppress TID leakage in compact NMOS layouts while preserving circuit density.

Uniform trench-sidewall insulation and segmented upper electrodes reduce gate-source capacitance while easing split-gate MOSFET fabrication.

Separate read and write ports in an 8T FinFET SRAM cell isolate the bit cell, reducing read disturbs while preserving stable data without refresh.

A sacrificial fill and ceramic infiltration approach forms flat, sub-10 nm contact isolation in narrow semiconductor trenches where conformal liners fall short.

Ferroelectric polarization domains create non-volatile lateral p-n junctions in 2D materials without fixed gates or defect-prone doping.

Inward-bowed gate spacers enable fuller metal gate deposition in dense FinFET regions, reducing voids and lowering gate resistance.

Pre-positioned FEOL interconnects expose backside contact surfaces for direct routing, avoiding TSV etching while reducing process time and complexity.

A conformal sacrificial layer protects the gate dielectric during annealing, enabling defect repair and less over-etching in narrow FinFET gaps.

Stacked metal bias wiring overlaps transistor regions to strengthen thermal coupling, stabilize gain, and improve RF amplifier heat balance.

A high-k gate stack with metal and polysilicon layers raises gate capacitance while limiting leakage and gate resistance in scaled MOS transistors.

Quantum dots and an inorganic bank structure improve light capture in small image-sensor pixels while reducing dark noise and boosting signal-to-noise ratio.

Separating photodiodes and transistors into stacked semiconductor layers boosts light capture, cuts noise, and avoids microlens cross-talk.