Stacked Decoupling Capacitors in Semiconductor Devices
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Solution Overview
Problem
Semiconductor memory devices face challenges in achieving high capacitance in a limited area for decoupling capacitors, particularly in high-integration and high-speed applications, where existing technologies result in reduced capacitance values due to increased noise filtering demands and separate fabrication processes that incur costs.
Innovation Solution
A semiconductor device with a stacked capacitor cluster, where multiple decoupling capacitors are connected in parallel, utilizing insulation and conduction layers formed on different transistor layers, including gate oxide and top gate insulation layers, to enhance capacitance without increasing layout size, allowing for reduced capacitor size without compromising capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If decoupling capacitors are disposed on the peripheral circuit region to filter noise, then noise filtering capability is improved, but the capacitance per unit area decreases due to limited available area
Solution Approach 1:
The patent transitions from planar decoupling capacitors to vertically stacked three-dimensional capacitors. Multiple capacitor layers are stacked in the vertical dimension, allowing multiple capacitive elements to occupy the same footprint area. This dimensional transition enables significantly higher total capacitance within the limited peripheral circuit region while maintaining effective noise filtering capability.
Solution Approach 2:
The patent implements nested capacitor structures where multiple capacitor layers are stacked one on top of another, with each layer containing capacitor elements that are electrically connected in parallel. The capacitors are nested within the vertical space above the peripheral circuit region, maximizing the use of available three-dimensional space to achieve high capacitance density.
2Device complexity
If separate deposition process is used for second and third polysilicon electrodes in multilayer decoupling capacitor, then capacitor structure is achieved, but manufacturing cost increases
Solution Approach 1:
The patent merges the formation of the third polysilicon electrode with the gate electrode formation process of memory cell transistors. Both structures are fabricated simultaneously in the same deposition process without requiring separate masking steps for the peripheral circuit region. This consolidation eliminates the need for additional deposition processes and reduces manufacturing complexity while maintaining the multilayer capacitor structure.
Solution Approach 2:
The third polysilicon electrode serves dual functions: it forms the upper electrode of the decoupling capacitor in the peripheral circuit region and simultaneously forms the gate electrode of memory cell transistors in the memory cell region. This multi-functional design allows a single deposition process to create both structures, reducing manufacturing steps and costs.
3Ease of manufacture
If MOS type capacitor is used with gate oxide layer as dielectric, then capacitor fabrication is simplified, but capacitance value is insufficient for high integration applications
Solution Approach 1:
The patent maintains the simple MOS capacitor structure using gate oxide layer as dielectric but compensates for insufficient capacitance by stacking multiple capacitor layers in the vertical dimension. The capacitance values of individual MOS capacitors are added together through parallel electrical connections, achieving high total capacitance while preserving fabrication simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases capacitance in a compact layout, reducing noise filtering losses and manufacturing costs by integrating decoupling capacitors within the same process as memory cells, maintaining high integration and speed requirements.
Implementation Method 1
A gate oxide layer of the MOS transistor is used as a dielectric layer
Implementation Method 2
stacked decoupling capacitors... increases capacitance in a compact layout
Data Source
AI summary
A semiconductor device having transistors formed on different layers of a stack structure includes a stacked capacitor cluster, wherein a stacked capacitor of the stacked capacitor cluster includes an insulation layer of a transistor of the semiconductor device, and at least a first conduction layer and a second conduction layer disposed above and below the insulation layer, wherein the stacked capacitor is a decoupling capacitor of the stacked capacitor cluster connected in parallel between a first line and a second line.