Compact Rad-Hard NMOS Layout for TID Leakage Suppression
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Solution Overview
Problem
Semiconductor devices, particularly NMOS transistors, are susceptible to Total Ionizing Dose (TID) radiation, leading to increased power dissipation and operational failures due to radiation-induced leakage, which existing technologies struggle to mitigate effectively in advanced CMOS technologies without compromising circuit density and performance.
Innovation Solution
The design involves displacing segments of the n-type source/drain diffusion regions into the active region to create gap regions, preventing silicide formation, and optionally forming a moderately-doped p-type band along the field oxide edge to increase the threshold voltage of parasitic transistors, thereby reducing radiation-induced leakage while maintaining high circuit density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard linear-gate NMOS transistor design is used, then circuit density and performance are maintained, but radiation-induced leakage current increases due to parasitic edge transistors
Solution Approach 1:
The patent extracts and removes the harmful n-type doping from the critical gap region between the source/drain diffusion and the field oxide edge. By creating an undoped gap region through selective masking during the NSD implant process, the parasitic edge transistor channel is eliminated, preventing radiation-induced leakage current while maintaining the benefits of advanced CMOS scaling.
Solution Approach 2:
The patent applies local quality by creating a specific undoped gap region only where needed at the field oxide edge, while maintaining heavily-doped n-type source/drain regions in other areas. This localized modification targets the parasitic channel formation site without affecting the main transistor performance, achieving radiation hardness with minimal impact on circuit density.
2Reliability
If n-type source/drain diffusion regions are displaced to create gap regions, then radiation-induced leakage is reduced, but device area increases
Solution Approach 1:
The patent applies partial action by creating gap regions only at the critical field oxide edges where parasitic transistors form, rather than displacing the entire source/drain diffusion. The gap width is optimized to be sufficient to prevent parasitic channel formation (typically 0.1-0.5 micrometers) without unnecessarily increasing device area. This targeted approach achieves radiation hardness with minimal area penalty.
3Reliability
If guard rings and channel stops are used to reduce leakage, then radiation hardness improves, but circuit density decreases
Solution Approach 1:
The patent extracts and eliminates the need for additional guard rings and channel stops by directly addressing the root cause of parasitic edge transistor formation. Through selective removal of n-type doping at the field oxide edge during the NSD implant process, the parasitic channel is prevented from forming in the first place, achieving radiation hardness without requiring extra leakage mitigation structures that would reduce circuit density.
4Productivity
If advanced CMOS process nodes are used, then circuit performance and density improve, but susceptibility to TID radiation increases
Solution Approach 1:
The patent applies local quality by implementing a selective doping removal technique that targets only the critical region at the field oxide edge in advanced CMOS processes. The gap region is created precisely where parasitic transistors form due to scaling effects, allowing the use of advanced CMOS nodes for high circuit density while locally mitigating TID susceptibility through the undoped gap that prevents parasitic channel formation.
Data Source
AI summary
Compact radiation-hardened NMOS transistors permitting close spacing for high circuit density can be fabricated using modern commercial foundry processes incorporating lightly-doped drain (LDD) and silicidation techniques. Radiation-induced leakage currents in parasitic field oxide transistors are reduced by spacing diffusions away from field oxide edges under the gate, forming gap regions from which n-type dopants and silicide formation are excluded using blocking patterns in the layout. P-type implants along these field oxide edges further increase radiation tolerance. Dimensions can be tailored to permit tradeoffs between radiation tolerance, breakdown voltage, and circuit density. Compact layouts for series-connected NMOS transistors are provided and applied to high-density rad-hard circuits. Methods for fabricating devices having these features are also provided, requiring minimal adaptation of standard processes. These designs and processes allow a mix of integrated circuits having differing levels of tolerance to total ionizing dose on the same semiconductor wafer.