Semiconductor Interconnect Resistance Reduction via Segmented Bonding
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Solution Overview
Problem
In semiconductor devices, the on-resistance is influenced by both transistor and interconnect components, with existing technologies facing challenges in effectively reducing the interconnect resistance component, particularly in devices using compound semiconductor layers as channels.
Innovation Solution
The semiconductor device configuration includes multiple transistor units with strategically arranged interconnects and bonding members connected at multiple points, allowing for increased interconnect width and reduced resistance by distributing connections between transistor units and bonding wires, thereby lowering the parasitic resistance component.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the number of connecting points of the wire is increased, then the delay time of transistor response is shortened, but the resistance component of the interconnect increases
Solution Approach 1:
The patent divides the interconnect structure into multiple segments: multiple interconnects (first, second, third, fourth interconnects) arranged in a specific pattern, with multiple bonding members (first, second, third, fourth bonding members) connecting at multiple points. This segmentation allows current to distribute through multiple parallel paths, reducing overall resistance while maintaining fast response time.
Solution Approach 2:
The patent combines multiple interconnects and bonding members into an integrated structure where the first and third interconnects extend between transistor units, while the second and fourth interconnects extend on opposite sides. Multiple bonding members connect to these interconnects at multiple points, creating a merged network that simultaneously achieves low resistance and fast response.
2Reliability
If the interconnect width is increased, then the resistance component is reduced, but the device area increases
Solution Approach 1:
The patent utilizes two-dimensional arrangement of interconnects (first, second, third, fourth interconnects) and bonding members across the device area. Instead of increasing width in one dimension, the solution distributes connections across multiple dimensions and locations, achieving resistance reduction through spatial distribution rather than dimensional expansion.
Solution Approach 2:
The interconnect structure is segmented into multiple thin interconnects (first, second, third, fourth interconnects) arranged in a specific pattern, with multiple bonding members connecting at distributed points. This segmentation allows the use of thinner individual interconnects while achieving equivalent or better resistance performance through parallel conduction paths, thereby reducing overall device area.
Data Source
AI summary
A source interconnect and a drain interconnect are alternately provided between a plurality of transistor units. One bonding wire is connected to a source interconnect at a plurality of points. The other bonding wire is connected to a source interconnect at a plurality of points. In addition, one bonding wire is connected to a drain interconnect at a plurality of points. In addition, the other bonding wire is connected to a drain interconnect at a plurality of points.