U-CMOS Logic Using Double-Gate n-Channel Transistors
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Solution Overview
Problem
Conventional CMOS devices face challenges due to the disparity in electron and hole mobilities, leading to larger PMOSFET transistor sizes and increased chip costs, as well as complex circuit layouts, especially in semiconductors with high electron mobility where hole mobility is significantly lower.
Innovation Solution
The implementation of Unipolar CMOS (U-CMOS) logic, which utilizes either all n-type or all p-type channels by replacing conventional p-channel transistors with n-channel transistors having negative threshold voltages, allowing for the use of enhancement-mode or accumulation-mode FETs with separate front and back channels to control current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional CMOS devices use both n-type and p-type channels to achieve complementary logic operation, then low standby power consumption is maintained, but device complexity increases and manufacturing cost rises due to the need for larger PMOSFET transistor sizes to compensate for lower hole mobility
Solution Approach 1:
The invention changes the threshold voltage parameter of n-channel transistors to negative values, enabling them to function as complementary devices traditionally requiring p-channel transistors. This parameter change allows all n-type channels to be used, eliminating the need for p-type channels and the associated size compensation, thereby reducing device complexity and manufacturing cost
Solution Approach 2:
The invention uses only n-type channels throughout the CMOS device, creating a homogeneous structure. By replacing the heterogeneous combination of n-type and p-type channels with a uniform n-type channel architecture, the invention simplifies manufacturing processes and reduces the complexity associated with matching different transistor types
2Speed
If conventional CMOS devices use p-channel transistors with negative threshold voltages to achieve current matching, then electron mobility advantages are lost, but circuit operation remains stable
Solution Approach 1:
The invention inverts the conventional approach by giving n-channel transistors negative threshold voltages instead of p-channel transistors. This inversion allows the device to exploit the higher electron mobility of n-type channels while maintaining complementary logic operation, thereby improving speed without sacrificing circuit stability
Solution Approach 2:
The invention changes the threshold voltage parameter of n-channel transistors from positive to negative values, enabling them to function in the complementary role traditionally filled by p-channel transistors. This parameter change allows the exploitation of higher electron mobility while maintaining reliable circuit operation
3Power
If conventional CMOS devices increase PMOSFET channel width to compensate for lower hole mobility, then current matching is achieved, but chip area increases and layout design becomes more complex
Solution Approach 1:
The invention uses only n-type channels with uniform, smaller dimensions throughout the CMOS device. This homogeneous approach eliminates the need for large PMOSFET channel widths, thereby reducing chip area while maintaining current matching and drive current performance
Solution Approach 2:
By changing the threshold voltage parameter of n-channel transistors to negative values, the invention enables these transistors to provide the complementary function with much smaller dimensions, eliminating the area penalty associated with large PMOSFET channels required for current matching
Data Source
AI summary
Improvements in Complementary Metal Oxide Semiconductor (CMOS) devices; in particular, field effect transistors (FETs) and devices using said transistors which are able to take advantage of the higher carrier mobility of electrons compared to holes by replacing the conventional p-channel transistor with an n-channel transistor having a double gate (or vice versa): Such a Unipolar CMOS (U-CMOS) transistor can be realised by adapting the source and/or the drain such that when the body region undergoes inversion at a first surface current, is able to flow between the drain and the source and when the body region undergoes inversion at a second surface current is not able to flow between the drain and the source. Various logic gates may be constructed using U-CMOS transistors.