Vertical Memory Transistor Layout for Buried Bit Line Integration
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Solution Overview
Problem
The integration level of transistors in existing memory technologies restricts storage density, and reducing transistor size to improve density leads to performance decline due to the narrow channel and short channel effects.
Innovation Solution
A method for forming a semiconductor structure involving a substrate with a sacrificial layer and active layer, where the active layer is patterned to form grooves and isolation layers, and bit lines are formed between active patterns, allowing for the creation of vertical transistors with buried bit lines to enhance storage density without compromising performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the channel size of the transistor is reduced to improve storage density, then the storage density of the memory is improved, but the performance of the transistor declines due to narrow channel effect and short channel effect
Solution Approach 1:
The patent transitions from planar transistors to vertical transistors, changing the dimensional orientation of the channel from horizontal to vertical. This allows the channel to extend in the depth direction rather than reducing its horizontal dimensions, thereby maintaining adequate channel width and length for proper transistor performance while achieving higher storage density through vertical stacking and three-dimensional integration.
Solution Approach 2:
The patent divides the transistor structure into multiple segments including source region, drain region, and channel region formed through sequential epitaxial growth. The active layer is divided into multiple active regions by grooves, and the transistor channel is segmented into first and second doped regions with an undoped channel region in between, allowing independent optimization of each segment's properties.
2Area of moving object
If the size of the transistor is reduced to improve storage density, then the storage density of the memory is improved, but the narrow channel effect and short channel effect cause performance degradation
Solution Approach 1:
The patent employs vertical transistors where the channel extends in the vertical dimension rather than reducing horizontal dimensions. The active layer thickness and channel length are controlled through epitaxial growth in the vertical direction, allowing small footprint transistors to maintain adequate channel dimensions for proper performance by utilizing the third dimension for channel formation.
Solution Approach 2:
The patent applies different doping concentrations and material compositions to different regions of the vertical transistor. The source and drain regions are heavily doped while the channel region remains undoped or lightly doped. The active layer may have different material compositions (e.g., SiGe gradient) in different vertical regions to locally optimize carrier mobility and threshold voltage characteristics.
Data Source
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AI summary
This application relates to a semiconductor structure and a method for forming the semiconductor structure and a memory. The method for forming the semiconductor structure includes: providing a substrate, where a sacrificial layer and an active layer located on the sacrificial layer are formed on the substrate; patterning the active layer and the sacrificial layer to form a groove, where the active layer and the sacrificial layer are divided into a plurality of active regions by the groove; forming a first isolation layer surrounding the active regions in the groove; patterning the active layer in the active regions to form a plurality of separate active patterns, where at least one of side walls or ends of the active patterns is connected to the first isolation layer; removing the sacrificial layer along an opening located between two adjacent one of the active patterns to form a gap between a bottom of the active patterns and the semiconductor substrate; and forming a bit line in the gap. The above method can reduce the planar size of a transistor and improve the storage density of the memory.