Semiconductor Device with Electron Trap Layer for Low Off-State Current
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in achieving low off-state current, low power consumption, miniaturization, high-speed writing and reading, long data retention, and eye-friendly display capabilities, particularly in transistors using oxide semiconductors like In—Ga—Zn oxide, which require improved electrical characteristics and reliability.
Innovation Solution
The semiconductor device incorporates a structure with a channel formation region and an electron trap layer, where the electron trap layer overlaps with the channel formation region, and a gate electrode that does not overlap with the channel formation region, allowing for controlled threshold voltage and reduced off-state current through electron trapping and tunneling mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a transistor including an oxide semiconductor is used, then power consumption is reduced and off-state current is lowered, but field-effect mobility and electrical characteristics need improvement
Solution Approach 1:
The patent applies parameter changes by controlling the threshold voltage of the oxide semiconductor transistor through negative fixed charge injection into the floating gate. This adjusts the electrical characteristics to achieve both low off-state current and improved field-effect mobility, resolving the contradiction between power consumption and electrical performance
2Loss of energy
If a floating gate with negative fixed charge is used to achieve normally-off characteristics, then off-state current is reduced, but device complexity increases
Solution Approach 1:
The floating gate structure serves multiple functions: it stores negative fixed charge to control threshold voltage, enables normally-off characteristics, and provides a pathway for electron tunneling. This multi-functionality reduces the need for additional components, thereby limiting the increase in device complexity while achieving low off-state current
3Productivity
If oxide semiconductor is deposited by sputtering for large substrate fabrication, then manufacturing scalability is improved, but capital investment and equipment complexity increase
Solution Approach 1:
The patent utilizes existing sputtering production equipment that is already established for manufacturing amorphous silicon or polycrystalline silicon transistors. By adapting the same deposition technique for oxide semiconductors, the invention avoids the need for entirely new equipment, thereby maintaining manufacturing scalability while limiting capital investment and equipment complexity increases
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in a semiconductor device with significantly reduced off-state current, low power consumption, and enhanced reliability, enabling high-speed operations and long data retention while maintaining eye-friendly display capabilities.
Implementation Method 1
allowing for controlled threshold voltage and reduced off-state current through electron trapping and tunneling mechanisms
Data Source
AI summary
A semiconductor device includes a first conductor, a second conductor, a first insulator, a second insulator, a third insulator, a semiconductor, and an electron trap layer. The semiconductor includes a channel formation region. The electron trap layer overlaps with the channel formation region with the second insulator interposed therebetween. The first conductor overlaps with the channel formation region with the first insulator interposed therebetween. The second conductor overlaps with the electron trap layer with the third insulator interposed therebetween. The second conductor does not overlap with the channel formation region.