Stacked Transistor Contact-Last Layout for Lower-Layer Protection
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Solution Overview
Problem
In semiconductor devices, stacking transistors can expose previously formed lower device layers to harmful conditions during processing, leading to potential damage and poor metal connections that increase resistance and risk of device failure.
Innovation Solution
The approach of forming stacked transistors with 'contact last' methodology, where metal contacts are created after subsequent transistor layers are formed, reduces exposure to damaging processes and ensures high-quality electrical connections by eliminating poor conductive couplings between metal contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are stacked one on top of the other to increase integration density, then the number of transistors per unit area increases, but the lower device layers are exposed to harmful processing conditions from subsequent upper layer formation
Solution Approach 1:
The patent inverts the conventional processing sequence by forming metal contacts to the lower transistor first, before forming the upper transistor. This reversal protects the lower transistor's metal contacts from damage during upper transistor processing while maintaining high integration density through stacked configuration.
Solution Approach 2:
The patent performs preliminary action by forming the metal contacts to the lower transistor and establishing their conductive connections before the upper transistor is formed. This ensures that the lower transistor's contacts are protected from subsequent processing steps that would otherwise expose them to harmful conditions.
2Ease of manufacture
If metal contacts are formed early in the process, then subsequent processing can proceed, but the metal contacts are exposed to high temperature annealing and other harmful conditions that can cause creeping or cracking damage
Solution Approach 1:
The patent inverts the conventional sequence by forming metal contacts after upper transistor processing is complete, rather than before. This eliminates exposure of the contacts to harmful high temperature annealing processes while maintaining manufacturing feasibility through the stacked transistor architecture.
3Manufacturing precision
If metal contacts are formed independently in separate processes, then each contact can be optimized, but poor conductive couplings between separate contacts increase resistance and may cause device failure
Solution Approach 1:
The patent merges the formation of metal contacts to the lower transistor with the overall contact formation process performed after upper transistor completion. This unified approach ensures proper conductive coupling between stacked transistor contacts while maintaining the ability to optimize contact formation parameters for the specific stacked architecture.
Data Source
AI summary
An apparatus is provided which comprises: a first transistor comprising a source region and a drain region with a channel region therebetween, a first dielectric layer over the first transistor, a second transistor comprising a source region and a drain region with a channel region therebetween, wherein the second transistor is over the first dielectric layer, a second dielectric layer over the second transistor, and a contact coupled to the source region or the drain region of the first transistor, wherein the contact comprises a metal having a straight sidewall that extends from through both the first and second dielectric layers. Other embodiments are also disclosed and claimed.