Gate-All-Around Common Metal Gates With Opposite Dipole Layers
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits below the 10 nanometer node poses challenges in maintaining mobility and short channel control, with conventional lithographic processes facing limitations in pattern dimension and spacing, particularly in gate-all-around architectures where isotropic wet etch processes lead to large N-P boundaries and reduced transistor density.
Innovation Solution
Implementing a common metal gate approach with opposite polarity dipole layers to achieve tight N-P boundaries and high transistor density, using a single band edge metal gate stack and opposite polarity dipoles for polarity flipping and threshold voltage tuning, reducing the need for multiple masks and etch operations, and replacing thicker workfunction metals with thinner dipole layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to pattern features in semiconductor stacks, then the critical dimension can be reduced, but the spacing between features increases
Solution Approach 1:
The patent transitions from planar 2D patterning to 3D gate-all-around structures, where the gate electrode completely surrounds the semiconductor channel in three dimensions. This dimensional change allows for tighter feature spacing while maintaining control over the critical dimension, as the gate wraps around the channel from top, bottom, and sidewalls, providing superior electrostatic control without requiring proportionally larger spacing between adjacent transistors
2Ease of manufacture
If isotropic wet etch processes are used in gate-all-around architectures, then the etching process is simpler, but large N-P boundaries are created reducing transistor density
Solution Approach 1:
The patent segments the gate electrode formation into distinct regions: n-type gates for NMOS transistors and p-type gates for PMOS transistors. By using anisotropic etching with directional control, the process creates sharp boundaries between n-type and p-type gate regions (tight N-P boundaries), preventing the large boundary regions that would result from isotropic etching and thereby maintaining high transistor density
Solution Approach 2:
The patent applies different etching characteristics to different regions of the gate electrode. The anisotropic etch process provides direction-dependent removal rates, enabling precise control over the gate boundary formation. This local control allows tight N-P boundaries at the interface between n-type and p-type gates while maintaining the desired gate-all-around geometry, directly addressing the transistor density issue
3Manufacturing precision
If multiple masks and etch operations are used to create different gate types, then precise gate patterning is achieved, but process complexity increases
Solution Approach 1:
The patent merges the gate electrode formation steps for n-type and p-type gates into a unified process flow. By using a single mask pattern and a controlled anisotropic etch process, both n-type and p-type gate regions are defined simultaneously in one etching operation, rather than requiring separate masking and etching steps for each gate type. This reduces process complexity while maintaining precise gate patterning through the directionality of the anisotropic etch
4Reliability
If thicker workfunction metals are used, then sufficient workfunction adjustment is achieved, but device dimensions increase
Solution Approach 1:
The patent changes the material composition and thickness parameters of the dipole layer to achieve the desired workfunction adjustment. By optimizing the dipole layer thickness and composition, sufficient workfunction control is obtained with a thinner layer than traditional workfunction metals, thereby reducing the vertical dimension of the gate stack while maintaining the necessary electrical characteristics for proper transistor operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables tight N-P boundary control, increased transistor density, and reduced complexity and cost in the metal gate flow, while maintaining high reliability and performance by avoiding the limitations of subtractive metal gate flows and aggressive etching in gate-all-around architectures.
Implementation Method 1
gate dielectrics with an opposite polarity dipole layer
Data Source
Figure 1A
Figure 1B
Figure 2
AI summary
Gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with one or more dipole layers are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires (108), and a second vertical arrangement of horizontal nanowires (110). A first gate stack (104B) is over the first vertical arrangement of horizontal nanowires (108), the first gate stack a PMOS gate stack having a P-type conductive layer (116A) on a first gate dielectric (112B) including a first N-type dipole material layer (NDT). A second gate stack (106B) is over the second vertical arrangement of horizontal nanowires (110), the second gate stack an NMOS gate stack having the P-type conductive layer (116B) on a second gate dielectric (114B) including the first N-type dipole material layer (NDT) and a second N-type dipole material layer (NDPF).