Thin-Film Transistor Structure With Embedded a-Si for Leakage Control
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Solution Overview
Problem
Amorphous silicon thin film transistors in display devices experience leakage current issues under high voltage, and existing solutions like modulating reference voltage or using extra electrodes lead to efficiency reductions or increased costs.
Innovation Solution
A thin film transistor structure is designed with a second amorphous silicon layer positioned within the gate insulation layer, overlapping the gate electrode and source/drain electrodes, which helps reduce leakage current by neutralizing electron-hole pairs under high voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common resolution method (modulating reference voltage, using two thin film transistors serially connected, or providing extra electrodes) is used to reduce leakage current, then leakage current problem is resolved, but efficiency is reduced or cost is increased
Solution Approach 1:
The patent embeds a second amorphous silicon layer within the gate insulation layer, creating a nested structure where the compensation layer is integrated inside the existing gate insulation layer rather than adding external components. This nested approach reduces leakage current without requiring additional transistors or electrodes, thereby maintaining efficiency.
Solution Approach 2:
The patent introduces a vertical dimension by placing the second amorphous silicon layer at a specific depth within the gate insulation layer (at a distance of 10-50 nm from the interface with the first amorphous silicon layer). This three-dimensional positioning enables effective leakage current compensation without adding lateral complexity or extra components that would reduce efficiency.
2Reliability
If extra electrodes or additional transistors are added to resolve leakage current, then leakage current problem is resolved, but device complexity is increased
Solution Approach 1:
The patent merges the leakage current compensation function with the existing gate insulation layer by integrating a second amorphous silicon layer within it. This consolidation combines multiple functions (insulation and leakage compensation) into a single integrated structure, avoiding the need for separate extra electrodes or additional transistors.
Solution Approach 2:
The gate insulation layer is designed to serve multiple functions: it provides electrical insulation between the gate electrode and the active layer, and simultaneously houses the second amorphous silicon layer that compensates for leakage current. This multi-functional design eliminates the need for dedicated leakage compensation components, reducing overall device complexity.
3Ease of manufacture
If the second amorphous silicon layer is positioned too far from the first amorphous silicon layer, then manufacturing is easier, but leakage current reduction effectiveness decreases
Solution Approach 1:
The patent optimizes the distance parameter between the second amorphous silicon layer and the first amorphous silicon layer, specifying it should be 10-50 nm. This precise parameter control ensures effective leakage current compensation while remaining compatible with standard manufacturing capabilities, balancing manufacturing ease with performance requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure effectively minimizes leakage current by positioning the second amorphous silicon layer in the gate insulation layer, enhancing the transistor's ability to manage high voltage conditions without efficiency or cost penalties.
Implementation Method 1
The structure effectively reduces leakage current by neutralizing electron-hole pairs under high voltage
Data Source
AI summary
A thin film transistor structure includes a gate electrode, a gate insulation layer, a first amorphous silicon layer, a source/drain electrode, and a second amorphous silicon layer. The gate insulation layer is located on the gate electrode. The first amorphous silicon layer is located on the gate insulation layer. The source/drain electrode is located on the first amorphous silicon layer. The second amorphous silicon layer is located in the gate insulation layer.