Deep Trench Capacitor Integration via Substrate Bonding
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Solution Overview
Problem
The integration of deep trench capacitors with logic circuits in semiconductor structures is challenging due to the need for separate fabrication of DRAM and logic areas, increased cycle time, and defects in the trench capacitor formation process, which complicates wafer fabrication as semiconductor technology advances and integration density increases.
Innovation Solution
A method and structure where a first substrate with buried plates and deep trench capacitors is formed, allowing for the integration of deep trench capacitors within the substrate, and a second substrate is bonded above with oxide layers to facilitate access for logic circuits, enabling the use of deep trench capacitors for memory and decoupling applications without the need for separate fabrication of DRAM and logic areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep trench capacitors are formed in traditional embedded DRAM structures, then memory elements can be created, but separate fabrication of DRAM and logic areas is required increasing device complexity
Solution Approach 1:
The patent merges DRAM capacitor fabrication with logic circuit fabrication by forming deep trench capacitors in a first substrate that is subsequently bonded to a second substrate containing logic circuits. This integration eliminates the need for separate fabrication processes for DRAM and logic areas, reducing device complexity while maintaining memory element functionality.
Solution Approach 2:
The patent segments the semiconductor structure into two separate substrates: a first substrate containing deep trench capacitors and a second substrate containing logic circuits. These substrates are fabricated independently and then bonded together, allowing each to be optimized separately while achieving integrated functionality.
2Reliability
If deep trench capacitors are formed during wafer fabrication, then memory elements are created, but cycle time increases
Solution Approach 1:
The patent performs preliminary action by forming deep trench capacitors in a first substrate before bonding it to a second substrate containing logic circuits. This allows the capacitor formation to occur in advance during a dedicated fabrication stage, rather than adding cycle time to the complete integrated structure fabrication process.
3Device complexity
If deep trench capacitors are formed in substrates with logic circuits, then integrated structures are achieved, but defects increase
Solution Approach 1:
The patent segments the integrated structure into two separate substrates that are fabricated independently with different processing requirements. The first substrate is optimized for deep trench capacitor formation while the second substrate contains logic circuits, eliminating the defect issues that arise from subjecting logic circuits to trench capacitor formation processes.
4Manufacturing precision
If separate fabrication processes are used for DRAM and logic areas, then each area can be optimized, but manufacturing complexity increases
Solution Approach 1:
The patent merges separately optimized substrates into a single integrated device by bonding a first substrate containing deep trench capacitors to a second substrate containing logic circuits. This allows each substrate to be manufactured with area-specific optimization while the bonding process integrates them into a unified structure that is easier to manufacture than fully integrated monolithic structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, reduces defects, and allows for efficient integration of deep trench capacitors, enhancing semiconductor structure performance by enabling their use in both memory and decoupling applications while maintaining the integrity of logic circuits.
Implementation Method 1
doping an upper part of the first substrate to form at least one buried plate in the first substrate
Data Source
AI summary
A semiconductor structure is disclosed in which, in an embodiment, a first substrate includes at least one buried plate disposed in an upper part of the first substrate. Each of the at least one buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.