FinFET Gate Spacer Reshaping for Lower Gate Resistance

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Solution Overview

Problem

The semiconductor industry faces challenges in reducing gate resistance (Rg) of FinFETs due to difficulties in fully depositing materials around metal gates, particularly in dense regions where dummy gate replacement is complex, leading to gaps or voids that increase resistance.

Innovation Solution

A spacer treatment process is applied to gate spacers, causing them to bow inward, which allows for more complete deposition of metal gates and reduces the formation of gaps or voids, thereby decreasing gate resistance by enabling better material deposition and contact with the substrate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional metal gate deposition is performed without spacer treatment, then the deposition process is simpler, but gaps or voids form around metal gates increasing gate resistance

Engineering Contradiction:
Improvegate resistanceVSAvoiddeposition process complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The gate spacers are treated with a spacer treatment process before metal gate deposition to pre-condition their surfaces. This preliminary action modifies the spacer surfaces to promote complete material deposition, preventing gaps or voids from forming during subsequent metal gate deposition, thereby reducing gate resistance without complicating the overall process

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The spacer treatment process acts as an intermediary step between conventional deposition processes and the metal gate formation. This intermediate treatment modifies the spacer surfaces to serve as better templates for complete material deposition, enabling full coverage around metal gates and reducing gate resistance

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If dummy gate replacement is performed in dense regions, then integration density is maintained, but complete material deposition becomes difficult leading to voids

Engineering Contradiction:
Improveintegration densityVSAvoidmaterial deposition completeness
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

In dense regions where dummy gate replacement is necessary, the spacer treatment process is applied beforehand to pre-condition the spacer surfaces. This preliminary modification ensures that subsequent material deposition can completely cover the complex geometries in dense regions, preventing voids while maintaining integration density

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The spacer treatment process is particularly important in dense regions where local geometry challenges prevent complete material deposition. By locally treating the spacer surfaces in these challenging areas, the process enables complete coverage where it is most needed, maintaining both integration density and deposition completeness

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11862638B2Semiconductor device and method
Publication Date: 2024.01.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11862638B2 patent drawing
  • US11862638B2 patent drawing
  • US11862638B2 patent drawing

AI summary

In an embodiment, a device includes: a first fin extending from a substrate; a second fin extending from the substrate; a gate spacer over the first fin and the second fin; a gate dielectric having a first portion, a second portion, and a third portion, the first portion extending along a first sidewall of the first fin, the second portion extending along a second sidewall of the second fin, the third portion extending along a third sidewall of the gate spacer, the third portion and the first portion forming a first acute angle, the third portion and the second portion forming a second acute angle; and a gate electrode on the gate dielectric.