Back-Channel-Etched IGZO TFT Substrate Yield
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Solution Overview
Problem
The manufacturing process of IGZO TFTs with a back-channel-etched structure faces challenges due to the weak bonding between Cu and SiOx, leading to curling and bubbling of the passivation layer, which affects the yield and stability of the TFT substrate.
Innovation Solution
A manufacturing method for a back-channel-etched TFT substrate is developed, where the source and drain are formed using a conductorized IGZO film with a strong bonding to SiOx, and a fluorine-free etching solution is used to remove the source-drain spacer without damaging the channel region, preventing curling and bubbling of the passivation layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Cu is used as source-drain material in IGZO TFT, then electrical conductivity is improved, but bonding strength with SiOx passivation layer deteriorates causing curling and bubbling
Solution Approach 1:
The patent employs a composite source-drain structure consisting of multiple material layers (Mo, Cu, and conductorized IGZO) where each layer contributes different properties. The Mo layer provides adhesion to the substrate, the Cu layer provides high electrical conductivity, and the conductorized IGZO layer provides strong bonding to the SiOx passivation layer while maintaining electrical conductivity, thus resolving the contradiction between conductivity and bonding strength.
Solution Approach 2:
The conductorized IGZO layer acts as an intermediary between the Cu layer and the SiOx passivation layer. It provides a transition zone that ensures strong bonding to the passivation layer while maintaining electrical conductivity, preventing the direct weak bonding between Cu and SiOx that causes curling and bubbling.
2Productivity
If conventional etching solution is used to remove source-drain spacer, then etching efficiency is improved, but channel region of active layer is damaged
Solution Approach 1:
The patent uses a fluorine-free etching solution that exhibits selective etching behavior with different etching rates for different materials. The solution is formulated to etch the source-drain spacer material (amorphous silicon) at a high rate while etching the IGZO active layer at a much lower rate, achieving both high etching efficiency and channel region protection through localized differential etching rates.
Solution Approach 2:
The patent changes the chemical composition parameters of the etching solution by removing fluorine compounds, which are known to aggressively etch IGZO. This parameter change (removing F-) reduces the etching rate on the channel region while maintaining adequate etching efficiency on the source-drain spacer through optimized solution chemistry and process conditions.
3Device complexity
If IGZO TFT with back-channel-etched structure is manufactured, then manufacturing complexity is reduced, but passivation layer stability deteriorates due to weak bonding
Solution Approach 1:
The patent uses a composite source-drain structure with conductorized IGZO as the top layer that provides strong bonding to the SiOx passivation layer. This composite structure maintains the simplified back-channel-etched manufacturing process while ensuring passivation layer stability through the strong IGZO-SiOx bonding interface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures a stable and reliable TFT substrate with improved bonding between the conductorized IGZO film and SiOx, preventing passivation layer curling and bubbling, and maintaining the integrity of the channel region, thereby enhancing the yield and performance of the TFT.
Implementation Method 1
the source and drain are formed using a conductorized IGZO film with a strong bonding to SiOx
Implementation Method 2
a fluorine-free etching solution is used to remove the source-drain spacer without damaging the channel region
Data Source
AI summary
A BCE TFT substrate includes a base substrate. A gate and a gate insulation layer are sequentially formed on the base substrate. An IGZO semiconductor layer is formed on the gate insulation layer to serve as an active layer. A source and a drain are disposed on the active layer and spaced from each other. Each of the source and drain is formed of a Mo layer, a Cu layer, and a conductorized IGZO film that are sequentially stacked on the active layer. A passivation layer is disposed on the source, the drain, and the active layer.