Stacked Combsheet FET Structure for Balanced CMOS Carrier Mobility
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Solution Overview
Problem
Current semiconductor devices, such as FinFETs and nanosheet FETs, exhibit differing mobilities for holes and electrons due to varying crystallographic plane orientations, leading to inefficiencies in semiconductor performance.
Innovation Solution
The development of a stacked combsheet field effect transistor (FET) with semiconductor nanosheets oriented in (100) crystallographic planes and fins oriented in (110) planes, which are integrally attached, to enhance both hole and electron mobility by creating additional (110) crystal plane surfaces beneficial for pFET hole mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If single crystallographic plane orientation is used, then manufacturing simplicity is maintained, but device performance deteriorates
Solution Approach 1:
The channel structure is segmented into multiple nanosheets with different crystallographic plane orientations. Specifically, some nanosheets have (100) planes for electron transport while others have (110) planes for hole transport, allowing independent optimization of electron and hole mobility in different segments of the device
Solution Approach 2:
The crystallographic plane orientation parameter is varied across different nanosheets within the same device structure. By changing this fundamental material parameter from (100) to (110) orientations in different segments, the device achieves optimized performance for both electron and hole transport while maintaining a relatively simple epitaxial growth manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the difference in mobility between pFET and nFET portions of CMOS FETs, increases effective width for improved mobility, and enhances pFET performance by utilizing additional (110) crystal plane surfaces.
Implementation Method 1
epitaxially growing, from the semiconductor substrate, a first plurality of stacked semiconductor nanosheets
Data Source
AI summary
An integrated circuit structure includes a first combsheet field effect transistor (FET), which includes: a semiconductor substrate; a first plurality of semiconductor nanosheets that extend along a <101> crystallographic direction and that have horizontal surfaces oriented in (100) crystallographic planes and vertical sidewalls oriented in (110) crystallographic planes; and a semiconductor fin that is integrally attached to the nanosheets, extends along the nanosheets, and has horizontal sidewalls oriented in (100) crystallographic planes and vertical surfaces oriented in (110) crystallographic planes.