Zig-Zag Active Regions for Gate Etch Bias Reduction
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Solution Overview
Problem
In semiconductor devices, especially in peripheral circuit regions of memory devices like DRAM, the loading effect causes etch bias issues, leading to reduced gate critical dimensions and process margins due to the inability to form dummy patterns in areas with insufficient spacing, resulting in defects and non-uniform line widths.
Innovation Solution
The semiconductor layout is modified with alternating recesses and protrusions in a zig-zag pattern on active regions, allowing for narrower gaps between gate patterns and increasing pattern density, even without dummy patterns, thereby reducing etch bias and improving photolithography margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy patterns are added around isolated gates to reduce loading effect, then etch bias is reduced and gate CD is improved, but device layout complexity increases and space is consumed
Solution Approach 1:
The patent applies local quality by making the active region width vary locally - wider in peripheral circuit regions where isolated gates exist and narrower in cell regions with dense gates. This local variation in active region dimensions compensates for the loading effect without requiring dummy patterns, thus improving gate CD while avoiding increased layout complexity.
2Stability of the object's composition
If larger spacing gap is designed between gates in peripheral circuit region, then isolation is improved, but loading effect increases and gate CD deteriorates
Solution Approach 1:
The patent changes the parameter of active region width to resolve the contradiction. By making the active region wider in peripheral regions, the patent maintains adequate gate isolation while providing sufficient pattern density to reduce loading effect during etching, thus preserving gate CD without compromising isolation.
3Area of stationary object
If narrower gap between active regions is used, then area is reduced, but dummy patterns cannot be formed due to insufficient spacing
Solution Approach 1:
The patent applies local quality by differentiating active region dimensions between peripheral and cell regions. In peripheral regions, the active region is made wider to enable sufficient spacing for pattern formation without dummy patterns, while in cell regions, the narrower active region is maintained to minimize area, thus resolving the contradiction between area reduction and manufacturing precision.
Data Source
AI summary
A semiconductor device having an improved gate process margin includes two active regions spaced apart from each other on a semiconductor substrate and respectively having bent sides with recesses and protrusions corresponding to each other, and two line-shaped gate patterns respectively formed in the longitudinal directions of the active regions. A gap at which the two gate patterns are spaced apart from each other by the recesses and the protrusions in the active regions is relatively narrower by a width difference between the recesses and the protrusions.