RF Switch Gate Oxide Stress Reduction via Voltage Divider
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional RF switches face challenges in achieving low insertion loss, high isolation, and linearity, especially in high-power applications, due to parasitic capacitance and low-resistivity substrates in CMOS technology, making it difficult to produce switches with fast switching times and high power handling capabilities.
Innovation Solution
The use of a triple-well NMOS transistor with a voltage divider circuit, where the gate terminal is connected to a voltage divider output, allowing the transistor to operate with reduced oxide stress and maintaining power handling capability, even at higher voltages, by ensuring the gate voltage is always above the threshold, thereby reducing voltage stress and enabling faster switching times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional CMOS technology is used for RF switches, then manufacturing cost is reduced and integration compatibility is improved, but parasitic capacitance and low-resistivity substrates cause poor isolation and limited power handling capability
Solution Approach 1:
The patent segments the substrate into multiple regions with different resistivity characteristics. A high-resistivity region is created beneath the switch transistor to reduce parasitic capacitance and improve isolation, while maintaining compatibility with standard CMOS manufacturing processes for cost-effectiveness.
Solution Approach 2:
The patent applies local quality by creating a high-resistivity substrate region specifically beneath the RF switch transistor, while other regions of the substrate maintain standard CMOS characteristics. This localized modification improves isolation performance without requiring entire substrate redesign, preserving manufacturing cost benefits.
2Power
If higher voltages are applied to improve power handling capability, then power handling is improved, but oxide stress on the gate increases reducing device reliability
Solution Approach 1:
The patent changes the substrate resistivity parameter locally to reduce parasitic capacitance, which allows the switch to achieve better isolation and power handling at lower gate voltages. This parameter modification enables high power handling capability without proportionally increasing oxide stress on the gate.
Solution Approach 2:
The high-resistivity substrate region acts as an intermediary that reduces parasitic capacitance between the transistor and substrate. This intermediary structure improves power handling capability by reducing unwanted coupling, allowing lower operating voltages that decrease oxide stress while maintaining power handling performance.
3Loss of time
If switching speed is increased to improve switching time, then switching time is reduced, but parasitic capacitance causes signal distortion and reduces linearity
Solution Approach 1:
The patent segments the substrate to create a high-resistivity region that minimizes parasitic capacitance. This segmentation enables faster switching times by reducing capacitive loading while maintaining signal linearity by reducing parasitic coupling effects during the switching transition.
Solution Approach 2:
By changing the substrate resistivity parameter in the region beneath the transistor, the patent reduces parasitic capacitance values. This parameter change enables faster switching speeds while preserving signal linearity, as the reduced parasitic capacitance minimizes distortion during rapid voltage transitions.
Data Source
AI summary
A RF switch circuit includes a voltage divider circuit and a semiconductor device. The semiconductor device has an activated state and a deactivated state. The voltage divider circuit has an input terminal connected to a first line and an output terminal connected to a second line. The first line is connected to a power source. A gate terminal of the semiconductor device is connected to the second line. In the activated state, a source terminal and a drain terminal of the semiconductor device are each selectively connected to ground. In the deactivated state, the source terminal and the drain terminal of the semiconductor device are each selectively connected to the power source.