Nanowire Internal Spacer Integration for Short-Channel Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As integrated device manufacturers shrink transistor feature sizes to achieve greater circuit density and higher performance, there is a need to manage transistor drive currents while reducing short-channel effects, parasitic capacitance, and off-state leakage, which existing technologies struggle to address effectively in next-generation devices.
Innovation Solution
The implementation of nanowire transistors with internal spacers formed from insulative, low-k dielectric material between the source/drain and channel regions, which reduces overlap capacitance and leakage by isolating the gate structure from the source/drain contacts, and the method of forming these spacers involves depositing material in dimples created adjacent to the channel region and transforming it to enhance etch selectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor feature sizes are shrunk to achieve greater circuit density, then circuit density is improved, but short-channel effects and off-state leakage increase
Solution Approach 1:
The gate structure is segmented into multiple sections along the channel length, with each section independently controlling a portion of the channel. This segmentation allows differentiated voltage control to suppress short-channel effects at different locations while maintaining overall high density
Solution Approach 2:
Intermediate conductive structures are introduced between the source/drain regions and the gate, serving as mediators to control the electric field distribution. These intermediaries help manage the harmful short-channel effects by creating potential barriers that prevent carrier leakage while preserving the scaled dimensions
2Productivity
If feature sizes are reduced to increase circuit density, then circuit density is improved, but parasitic capacitance increases
Solution Approach 1:
The transistor structure transitions from planar to three-dimensional configurations, with gates wrapping around nanowire channels in multiple dimensions. This dimensional change increases the effective gate control area without proportionally increasing parasitic capacitance, as the gate surface contacts the channel from multiple directions rather than just one plane
Solution Approach 2:
Different regions of the gate structure are assigned different electrical characteristics and control voltages. The gate sections adjacent to source/drain regions have optimized capacitance properties to minimize parasitic effects, while maintaining strong control over the channel region
3Power
If drive currents are increased to improve performance, then performance is improved, but off-state leakage increases
Solution Approach 1:
The gate structure enables dynamic and independent voltage control at different positions along the channel. During off-state, intermediate structures can be biased to create potential barriers that dynamically block leakage currents. During on-state, the same structures are biased to minimize resistance for drive currents, achieving selective dynamic control of current flow
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces overlap capacitance and leakage, improving the control of short-channel effects and enhancing the management of drive currents in nanowire transistors, thereby addressing the challenges of parasitic capacitance and off-state leakage.
Implementation Method 1
internal spacers formed from insulative, low-k dielectric material between the source/drain and channel regions, which reduces overlap capacitance and leakage by isolating the gate structure from the source/drain contacts
Implementation Method 2
the method of forming these spacers involves depositing material in dimples created adjacent to the channel region
Data Source
AI summary
A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.